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CPU reference: GGUF reader, dequant, Qwen3 fp32 forward, golden test - #1
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The fp32 oracle the NPU and GPU backends will be tested against. - engine/core: mmap GGUF v2/v3 reader, F32/F16/BF16/Q8_0 dequant, model config from GGUF metadata (only verified archs accepted), thread pool. - engine/backends/cpu: Qwen3 decoder in fp32. Load fails on any missing, misshaped or unused tensor. - tests: GGUF and dequant unit tests on synthetic data (run in CI); golden_cpu compares against HF transformers fp32 logits. - tools/golden/make_golden.py writes the golden logits. Qwen3-0.6B, 36 positions teacher-forced: argmax 36/36, worst KL 1.3e-10 (gate 1e-6). Deliberately broken RoPE and k-norm builds both fail the gate. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Sep 22, 2026
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…bases our commits third_party/ds4 moves to 1bit-MONSTER/ds4 1bit/main (a7f2e1e): upstream antirez/ds4 main plus our 1BP v5 reader, converter and checker (ds4 #1). bump-ds4.yml now rebases the commits we carry onto upstream main, tags the old tip and opens the pin PR, as bump-llama-vulkan does. 1bit serve recognises a 1BP package by its magic and serves it on ds4, --device auto included. docs/dwarfstar.md and NOTICE follow. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…bases our commits third_party/ds4 moves to 1bit-MONSTER/ds4 1bit/main (a7f2e1e): upstream antirez/ds4 main plus our 1BP v5 reader, converter and checker (ds4 #1). bump-ds4.yml now rebases the commits we carry onto upstream main, tags the old tip and opens the pin PR, as bump-llama-vulkan does. 1bit serve recognises a 1BP package by its magic and serves it on ds4, --device auto included. docs/dwarfstar.md and NOTICE follow. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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…bases our commits (#196) third_party/ds4 moves to 1bit-MONSTER/ds4 1bit/main (a7f2e1e): upstream antirez/ds4 main plus our 1BP v5 reader, converter and checker (ds4 #1). bump-ds4.yml now rebases the commits we carry onto upstream main, tags the old tip and opens the pin PR, as bump-llama-vulkan does. 1bit serve recognises a 1BP package by its magic and serves it on ds4, --device auto included. docs/dwarfstar.md and NOTICE follow. Co-authored-by: bong-water-water-bong <bong-water-water-bong@1bit.gg> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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…y_register_host, because the trigger registers with coherence unset Reading the dump further changed what #315 needs most, so the queue's first item is superseded. NEW #1: iree_hal_streaming_memory_register_host (libhrx/src/binding/common/memory.c, called from the in-tree hipHostRegister). It is ABSENT from the dump - no JSON and not among the 103 failures, so it was never captured rather than captured-and-failed. It outranks hrx_allocator_virtual_memory_map because: (1) it decides the COHERENCE DEFAULT for host-registered memory, and the register path has explicit flags (FLAG_HIP_COHERENT 1<<30, FLAG_HIP_NON_COHERENT 1<<31) unlike the pool path; (2) the #315 trigger registers with the flag UNSET - evictonly.hip calls hipHostRegister(b, bytes, hipHostRegisterDefault), flags=0, and the decompiled hipHostRegister (captured, OK) overwrites its own READ_ONLY default with 0 & (...) = 0, so it passes FLAG_DEFAULT = 0, neither coherence bit set - so what the trigger's memory IS depends entirely on what register_host does with 'unspecified'; (3) if that default is non-coherent, the eviction churn operates on non-coherent registered memory and 'coherence does not matter' is wrong for a second independent reason. Order: register_host, then virtual_memory_map/protect/unmap, then the hrx_fence_* and hrx_*_synchronize families already listed. Also asks for the HIP hipHostRegister flag values from the headers so the (flags & 8) branch can be confirmed against the header rather than inferred.
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The fp32 correctness oracle. Every NPU and GPU backend will be gated against it.
What
engine/core: mmap GGUF v2/v3 reader, F32/F16/BF16/Q8_0 dequant, model config from GGUF metadata (refuses unverified architectures), thread pool.engine/backends/cpu: Qwen3 decoder in fp32. Loading fails on any missing, misshaped or unused tensor.tests/: GGUF and dequant unit tests on synthetic data (run in CI);golden_cpuagainst HF transformers fp32 logits.tools/golden/make_golden.py,docs/cpu-reference.md.Results (Strix Halo, Qwen3-0.6B BF16 GGUF vs transformers fp32 eager)
Negative controls: RoPE Normal instead of Neox → 17/36 mismatches, KL 7.9; k-norm skipped → 34/36, KL 24.9. Both fail.
Test plan
ctestlocally (unit tests) and on strixhalo with-DENGINE_GOLDEN_MODEL/DIR(3/3 pass)-Wall -Wextra -Wpedantic, zero warnings (g++ 15.2)Not in this PR: tokenizer, K-quants, a longer-context golden.
🤖 Generated with Claude Code