diff --git a/config/hrx-long-prompt-validated-pin.config b/config/hrx-long-prompt-validated-pin.config
index 3ed466981..dacde59f7 100644
--- a/config/hrx-long-prompt-validated-pin.config
+++ b/config/hrx-long-prompt-validated-pin.config
@@ -12,4 +12,4 @@
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 # See the License for the specific language governing permissions and
 # limitations under the License.
-2ab3114966a4da12b5828e27f6cf705a5ebb7ee0
+82804197bcbe060b1371d6548337fdc842034cdd
diff --git a/config/hrx-system-hold.config b/config/hrx-system-hold.config
index 19c8902fa..6ede881a6 100644
--- a/config/hrx-system-hold.config
+++ b/config/hrx-system-hold.config
@@ -54,4 +54,10 @@
 # page is refused instead of faulting. Nothing else moves: same pin line, same AMD core, the
 # #1535 question stays where it was, and the long-prompt check passed at this commit
 # (tests/hrx_long_prompt.py PASS twice, 7082-token prompt, needle 7341).
-2ab3114966a4da12b5828e27f6cf705a5ebb7ee0
+# 2026-10-18, engine#315 candidate 1: the hold names 82804197b, which is 2ab311496 plus
+# hrx-system#8 - util/no_svm_gate.c, HRX_ALLOW_NO_SVM=1 lets the amdgpu HAL open a ROCr that
+# reports no SVM (HSA_USE_SVM=0), so serve can put the CWSR save area in GTT on a CWSR-on box
+# (app/hrx_cwsr.h). Unset, nothing changes. Same pin line, same AMD core.
+# The long-prompt check passed at this commit (tests/hrx_long_prompt.py PASS twice, 7082-token
+# prompt, needle 7341, 2026-10-18 on strixhalo).
+82804197bcbe060b1371d6548337fdc842034cdd
diff --git a/docs/hrx.md b/docs/hrx.md
index 692a91c44..4d26d5190 100644
--- a/docs/hrx.md
+++ b/docs/hrx.md
@@ -47,7 +47,9 @@ HRX0:    AMD Radeon 8060S Graphics (Node 1) (gfx1151)
   extent instead of skipping the check); engine#410 (`libhip_intercept` covers every HIP symbol the
   backend exports, init is idempotent); engine#401 (libhsa no longer opens `/dev/accel` in GPU-only
   processes); #6 (`generate_stubs.py` takes signatures from `api.h`, so `--check` is trustworthy;
-  regenerated `stubs_generated.c`); and our fix for the long-context attention miscompile
+  regenerated `stubs_generated.c`); #8 (engine#315: `HRX_ALLOW_NO_SVM=1` lets the amdgpu HAL open a ROCr
+  that reports no SVM, which `1bit serve` uses to put the CWSR save area in GTT on a CWSR-on box;
+  unset, nothing changes); and our fix for the long-context attention miscompile
   ([ROCm/hrx-system#1535](https://github.com/ROCm/hrx-system/issues/1535)): AMD's newer Loom no longer
   reaches the defect on our prompts, but its multi-unit live-out guard is still in
   `unit_liveness_builder.c`, so we keep removing it. The GFX11 wave64 lane-mask backport (#313) is
diff --git a/third_party/hrx-system b/third_party/hrx-system
index 2ab311496..82804197b 160000
--- a/third_party/hrx-system
+++ b/third_party/hrx-system
@@ -1 +1 @@
-Subproject commit 2ab3114966a4da12b5828e27f6cf705a5ebb7ee0
+Subproject commit 82804197bcbe060b1371d6548337fdc842034cdd