diff --git a/crates/fbuild-build-mcu/src/ch32v/README.md b/crates/fbuild-build-mcu/src/ch32v/README.md
index 25a2654a..fd2e8276 100644
--- a/crates/fbuild-build-mcu/src/ch32v/README.md
+++ b/crates/fbuild-build-mcu/src/ch32v/README.md
@@ -1,3 +1,15 @@
 # CH32V Platform Build Support
 
 Build orchestrator for WCH CH32V RISC-V MCUs. Uses xPack riscv-none-elf-gcc toolchain and OpenWCH Arduino core framework.
+
+The V303/V307 board definitions use the vendor hard-float profile
+(`rv32imafcxw`/`ilp32f`, normalized to `rv32imafc_zicsr`). This intentionally
+differs from Community-PIO-CH32V's soft-float defaults. The vendor builder also
+uses `-msave-restore -msmall-data-limit=8 -fno-use-cxa-atexit`; fbuild keeps
+`-msmall-data-limit=0` and omits those flags, so reference-build flash-size
+comparisons should record that code-generation difference.
+
+Some board packages reuse the nearest upstream pin-map variant because the
+pinned OpenWCH core does not ship a dedicated map: V208 uses the V203 map,
+X035 uses the G8U map, and V103 uses the R8T6 map. These are intentional
+registry fallbacks, not claims that the physical pinouts are identical.
diff --git a/crates/fbuild-build-mcu/src/ch32v/orchestrator.rs b/crates/fbuild-build-mcu/src/ch32v/orchestrator.rs
index fcf50b42..80e60c3f 100644
--- a/crates/fbuild-build-mcu/src/ch32v/orchestrator.rs
+++ b/crates/fbuild-build-mcu/src/ch32v/orchestrator.rs
@@ -90,7 +90,10 @@ impl BuildOrchestrator for Ch32vOrchestrator {
                 .unwrap_or(after_prefix.len());
             format!("ch32{}", &after_prefix[..series_end])
         } else {
-            "ch32v003".to_string()
+            return Err(fbuild_core::FbuildError::ConfigError(format!(
+                "CH32V board MCU must start with `ch32`; got `{}`",
+                ctx.board.mcu
+            )));
         };
         let system_series = series_to_system_dir(&series);
 
diff --git a/crates/fbuild-toolchain/src/toolchain/riscv.rs b/crates/fbuild-toolchain/src/toolchain/riscv.rs
index 497d7cb6..f10be4e8 100644
--- a/crates/fbuild-toolchain/src/toolchain/riscv.rs
+++ b/crates/fbuild-toolchain/src/toolchain/riscv.rs
@@ -251,7 +251,7 @@ impl Toolchain for RiscvToolchain {
 /// A platform-specific RISC-V toolchain package entry.
 struct RiscvPlatformPackage {
     filename: &'static str,
-    /// SHA-256 checksum. `None` = skip verification (not yet captured).
+    /// SHA-256 checksum for the immutable upstream release asset.
     checksum: Option<&'static str>,
 }
 
@@ -262,32 +262,28 @@ fn all_platform_packages() -> [(&'static str, RiscvPlatformPackage); 4] {
             "windows",
             RiscvPlatformPackage {
                 filename: "xpack-riscv-none-elf-gcc-14.2.0-3-win32-x64.zip",
-                // TODO: capture real checksum from Windows CI run
-                checksum: None,
+                checksum: Some("9bb15efdeca256532c4a83ce6462c7dc1f9cfebe1f1f43d581b2ad7d077209b6"),
             },
         ),
         (
             "macos",
             RiscvPlatformPackage {
                 filename: "xpack-riscv-none-elf-gcc-14.2.0-3-darwin-x64.tar.gz",
-                // TODO: capture real checksum from macOS CI run
-                checksum: None,
+                checksum: Some("8a6e699f12876152d6386e777675d94529ccc21a57224a69d973f676949a1687"),
             },
         ),
         (
             "linux-aarch64",
             RiscvPlatformPackage {
                 filename: "xpack-riscv-none-elf-gcc-14.2.0-3-linux-arm64.tar.gz",
-                // TODO: capture real checksum from aarch64 CI run
-                checksum: None,
+                checksum: Some("0c0551986e30174af55f245e1c3a86c45233fc793bf36586567f266ada6fdd98"),
             },
         ),
         (
             "linux-x86_64",
             RiscvPlatformPackage {
                 filename: "xpack-riscv-none-elf-gcc-14.2.0-3-linux-x64.tar.gz",
-                // TODO: capture real checksum from Linux x86_64 CI run
-                checksum: None,
+                checksum: Some("f574415b63f12b09bdd3475223ab492a465d23810646c90c13a4c3b676c83503"),
             },
         ),
     ]
diff --git a/docs/usb-cdc-control-line-matrix.md b/docs/usb-cdc-control-line-matrix.md
index c514789e..9fa83f92 100644
--- a/docs/usb-cdc-control-line-matrix.md
+++ b/docs/usb-cdc-control-line-matrix.md
@@ -143,6 +143,19 @@ Sources (captured 2026-06, primary source in Mandarin):
 - WCH CH340/CH341 datasheet —
   <https://www.wch.cn/downloads/CH340DS1_PDF.html>.
 
+### WCH — CH32V native USB CDC and WCH-LinkE CDC
+
+| Bit | Effect on device | Comment |
+|---|---|---|
+| DTR | informational / device-specific | The CH32V factory USB-ISP path does not use host DTR/RTS as a reset convention. Enter ISP with BOOT0/Download at reset. |
+| RTS | informational / device-specific | No documented host-driven reset convention for the native CH32V CDC or WCH-LinkE CDC interface. |
+
+- **Post-open safe default: `DTR=True, RTS=True`**. This is the same
+  conservative state used for unclassified WCH CDC devices.
+- WCH-LinkE's debug/DAP interface may enumerate separately from its CDC
+  endpoint; deployers should use the probe backend rather than infer reset
+  semantics from serial control lines.
+
 ### PJRC — Teensy USB-Serial (Teensy 3.x / 4.x)
 
 | Bit | Effect on device | Comment |