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Static analyzer for standard an ultra circuits #1086
Description
A mechanism that treats the whole circuit before finalization (in case of ultra) as a graph with additional information and looks at the following properties:
- How many independent subgraphs (real variables being vertices) there are
- Whether there are any unexpected variables only present in 1 gate (apart from known cases this signals and underconstrained circuit)
### Tasks
- [x] Create Initial implementation of static analyzer with lookup, arithmetic, sorted, elliptic gates taken care of
- [x] Create PR patch for the discovered issue
- [x] Finalize and clean up PR with initial implementation and with AES and SHA256 tests
- [x] Create tests for blake
- [x] Extend mechanism to Auxiliary and Poseidon gates
- [x] Create tests for cycle group
Activity
Rumata888 commentedon Mar 18, 2025
AztecProtocol/aztec-packages#12130