Meta: LPC port completion — Stage 3 fbuild-side items from FastLED #2845

[zackees]

Carved out from the closing of FastLED meta #2845 (Stage 3 fbuild-side items).

Background

The Stage 4 work on the FastLED side (LPC11Uxx clockless, LPC15xx clockless, APA102 SPI) shipped via FastLED #2872 + #2876. What remains on Stage 3 is split between hardware bring-up (covered at FastLED #2880) and fbuild software work, which lives here.

Items

3.1 — Real SystemInit for LPC845

FRO 30 MHz + PLL + flash wait states per NXP UM11029 §4. Currently a no-op stub in crates/fbuild-build/src/nxplpc/assets/startup_lpc845.S. The bit-bang cycle counts in FastLED clockless_arm_lpc.h derive from F_CPU = 30_000_000UL; without a real PLL config the LPC845 boots at 12 MHz IRC and timing is off by 2.5x. Hardware verification required.

3.2 — Real SystemInit for LPC804

UM11065 §4. Leave at 15 MHz default unless PLU clocking (FastLED #2848) requires a PLL boost. Document the choice in startup asm comments. Hardware verification required.

3.3 — Vector table expansion

Currently ships the ARMv6-M 16-entry system minimum. Add peripheral IRQs as drivers reach a state where they need them:

• DMA-end IRQ for the SCT + DMA-to-GPIO clockless driver (FastLED #2842 / #2850).
• SCT match IRQ for the SCT driver.
• USART RX for the AutoResearch UART hook (FastLED #2880, Stage 3.6).

3.4 — Per-chip mcu_config split in get_nxplpc_config

get_nxplpc_config currently ignores the mcu arg and returns shared config. Split when Stage 2b/2c flag divergence requires it: PLU defines for LPC804 (FastLED #2841 / #2848), FASTLED_LPC_PWM_DMA for LPC845 (FastLED #2842 / #2850).

3.7 — fbuild CI continue-on-error: true flip

Workflows at .github/workflows/build-lpc804.yml + build-lpc845.yml. Drop continue-on-error: true once 3.1 + 3.5 land and bash compile lpc845 --examples Blink is green end-to-end on real silicon.

3.8 — validate_boards.py reconciliation

Already partially filed at #421/#422 — that's the "boards in the fbuild-native registry not in the PIO source" case. Confirm the LPC845/LPC804 entries are reconciled as part of closing this meta.

Ownership

• 3.1, 3.2, 3.3, 3.4, 3.7, 3.8 — fbuild, all in crates/fbuild-build/src/nxplpc/ and crates/fbuild-config/assets/boards/json/.
• 3.5 (linker verification on hardware) — FastLED #2880.
• 3.6 (AutoResearch UART) — FastLED #2880.

Why a meta on the fbuild side

These six items have substantial cross-dependencies (3.3 depends on which drivers ship; 3.4 on which features they activate; 3.7 on 3.1 + hardware). Tracking them in a single fbuild meta is cleaner than scattered single-item issues against a partly-complete LPC port.

References

• FastLED meta #2845 — original cross-repo roadmap (closing as superseded)
• FastLED #2880 — hardware bring-up companion
• NXP UM11029, UM11065 — LPC8xx user manuals

🤖 Filed via Claude Code on behalf of the FastLED meta-#2845 close-out.

[zackees]

Status update on item 3.7

PR #453 just landed (closing a different, unrelated workflow-parse failure) and dropped the continue-on-error: true from both build-lpc804.yml and build-lpc845.yml — but for a reason orthogonal to 3.7's original framing:

continue-on-error is not in the allow-list of keywords for jobs that call a reusable workflow. With it set, the workflows failed at parse time with "workflow file issue" before any job ran — 30/30 of the most recent runs on each were red purely from that. PR #453 removes the unsupported keyword so the workflows now actually parse + execute.

Net effect on item 3.7:

• ✅ continue-on-error: true is gone (PR fix(ci): drop unsupported continue-on-error from LPC8xx workflows #453).
• ⏳ The underlying fbuild build step inside template_build.yml still fails fast with "Stage 2 required" for both lpc804 + lpc845, so the jobs go red on every push to main and on every PR. Expected pre-Stage-2 behaviour.
• 📌 The "non-blocking" intent of the original 3.7 is preserved by branch protection not listing these two workflows as required-checks — that's a repo-settings invariant, not a YAML knob.

So item 3.7's remaining work collapses to: once 3.1 + 3.5 land and bash compile lpc845 --examples Blink is green on real silicon, remove the early "Stage 2 required" guard from the LPC orchestrator's build step (likely in crates/fbuild-build/src/nxplpc/orchestrator/*) so these workflows can flip from "red by design" to "green by design". No further workflow-YAML changes needed.

Concrete pointer for the next visitor: search crates/fbuild-build/src/nxplpc/ for the "Stage 2 required" literal — that's the gate.

Surfaced by PR #454's CI run where the two Build NXP LPC* jobs are the only remaining reds and are working as intended.

🤖 Filed via Claude Code while triaging PR #454's CI.

[zackees]

Status survey — every shippable fbuild-side item is in main

Walked the code on main (HEAD 357629c6) for each item this meta tracks.

Item	Status	Where
3.1 LPC845 SystemInit	✅ shipped, with hardware-blocked TODO	crates/fbuild-build/src/nxplpc/assets/startup_lpc845.S:207 — programs flash wait states (1 WS) + sets SYSAHBCLKDIV=1 + latches MAINCLKSEL=FRO. The FRO-to-30 MHz reconfig has an explicit TODO(2845) comment gated on real-silicon validation.
3.2 LPC804 SystemInit	✅ shipped (intentionally minimal)	crates/fbuild-build/src/nxplpc/assets/startup_lpc804.S:206 — explicitly leaves FRO at the 15 MHz IRC reset default to match F_CPU=15000000UL in FastLED led_sysdefs_arm_lpc.h. Design-note comment explains why no PLL is configured.
3.3 Vector table expansion	✅ shipped	Both startup files emit 48 .word entries (16 ARMv6-M system + 32 LPC8xx peripheral IRQs) covering SPI / USART / I2C / SCT / ADC / DMA / PIN_INT / PLU. Driver-specific overrides happen via .weak aliases — the next driver that needs a new IRQ adds a strong handler, the table itself stays as-is.
3.4 Per-chip mcu_config split	✅ shipped	crates/fbuild-build/src/nxplpc/mcu_config.rs:86 (get_lpc804_config) + :102 (get_lpc845_config). Each layers chip-specific defines (__LPC804__ / __LPC845__ + the matching CPU_LPC* CMSIS id) on a shared base. Tests at :176 + :194 verify no leakage between chips.
3.7 Drop continue-on-error flip	✅ shipped via PR #453	The keyword was actually NOT in the supported-keyword list for jobs that call a reusable workflow — every push went red with "workflow file issue". #453 dropped it and replaced the comment with the docs-link to the allow-list. Non-blocking is now preserved via branch protection.
3.8 validate_boards.py reconciliation	✅ shipped	ci/validate_boards.py:66 (FBUILD_NATIVE_BOARDS frozenset) lists lpc845 + lpc804 with the rationale comment explicitly referencing this meta's item 8.

Out of scope here (tracked elsewhere)

• 3.5 linker verification on hardware → FastLED #2880 (cross-repo, hardware-blocked)
• 3.6 AutoResearch UART driver → FastLED #2880 (cross-repo)

What's left on item 3.1 (the only TODO)

The LPC845 SystemInit doesn't reconfigure the FRO to 30 MHz; it leaves the core at the FRO reset default (typically ~24 MHz post-divider). FastLED clockless_arm_lpc.h's bit-bang cycle counts derive from F_CPU=30_000_000UL, so timing on real silicon will be off by ~25% until a verified FRO-to-30 MHz sequence per UM11029 §4 is dropped in. That step needs an LPCXpresso845 on a bench and a logic-analyzer trace; the TODO in the code is explicit about that gate. Splitting it into its own follow-up isn't worth the issue-thrash — when the hardware shows up, the TODO is the single point to grep for.

Closing as resolved on the fbuild side.

🤖 Status surveyed via Claude Code; cross-referenced each item against the files cited.