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Rebased this proposal onto the refreshed CPU/Hybrid ROCm graph-safety PR (#378, head The conflict in Validation:
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Integrate FlashML-org#133, FlashML-org#134, FlashML-org#135, FlashML-org#378 and FlashML-org#491 before FlashML-org#587. Preserve the tested FlashML-org#378 handshake and runtime-only linkage, and retain the FlashML-org#134 installation document. Exclude CI and closed GGUF PR FlashML-org#136.
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Use upstream FlashML-org#638 and FlashML-org#134; integrate incremental FlashML-org#135 and FlashML-org#378 plus the updated standalone FlashML-org#491 before FlashML-org#587. Retain the probed FlashML-org#378 handshake and upstream installation document.
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Summary
Extract the shared Hybrid MoE decode schedule from
OffloadMoELayerintoHybridDecodeExecutor. This is now a standalone, single-commit refactor onmain(9b585b7), not a stack containing #378.statistics, CPU submit/sync order, and
FREETOKEN_HYBRID_OVERLAP=0behavior.supports_inactive_slotshandling in the layer:capable kernels receive
-1; other kernels get zero-weighted slot 0.test use Triton rather than an unrelated CUDA-only FlashInfer selection.
No changes to CPU kernels, CUDA/HIP synchronization, cache replacement policy,
or expert math. The short design note describes these boundaries.
Related: #350 and #378. This PR does not fix ROCm CPU/Hybrid graph safety;
#378 remains a separate change. Neither its implementation nor its validation
claims are included here.
Validation
One AMD Radeon AI PRO R9700 (gfx1201, 32 GiB); dual EPYC 9334; Ubuntu 24.04;
host kernel/driver
7.0.0-31-generic; PyTorch2.11.0+rocm7.14.0,HIP
7.14.60850, Triton3.7.1. Synthetic expert banks; no model checkpoint.Only one GPU was exposed to the container.
181 passed, 42 skipped, 5 deselected. The new file contributes 21 CPU
contract cases and 12 real BF16 Hybrid CPU/GPU cases. The existing CPU-executor
tests additionally cover BF16, NVFP4, MXFP4, DS-FP4 and Q4_0 eager computation;
this is not five-format Hybrid end-to-end coverage.
A supplemental local A/B harness compared the saved
mainlayer implementationagainst this branch using identical cache/kernels/CPU executor: 36 combinations
x 12 steps, bitwise-equal outputs and rewritten routing, identical cache state
and statistics. Batch sizes 1/4/8, fetch caps 0/1/8, overlap on/off and
router-weight-on-input on/off were exercised.
Local single-layer eager microbenchmark (not a shipped benchmark or model-serving
result): BF16, 3 layers, 8 experts, H=1024, I=512, top-k=2, fetch cap=1,
4 CPU workers, CPUs 32-39, warmup then 10 alternating A/B rounds of 128 calls.
Limits
validation in this revision. The four graph-replay tests and one slow test
were explicitly deselected above; graph support is inherited from main.
in HIP synchronization, including while executing the saved main path;
two runs were interrupted. The completed A/B and pinned-core final suite and
benchmark passed. This refactor does not claim to diagnose or fix those waits.
Ready for review as a focused orchestration refactor, not as a graph-safety fix
or a claim of zero overhead/full-model performance parity.