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[None][feat] Kimi K3: unlock the CUTEDSL MoE backend for NVFP4 SiTU - #19003
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Included review availability: Your plan provides up to 12 included reviews per hour; 10 remain after this review. WalkthroughKimi K3 NVFP4 now supports SiTU through CuteDSL, preserves explicit backend failures, adds resolver and kernel tests, and exposes backend selection in Python and Slurm launchers. ChangesKimi K3 SiTU backend support
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~45 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant KimiK3Launcher
participant LLM
participant BackendResolver
participant CuteDslFusedMoE
participant SiTUKernel
KimiK3Launcher->>LLM: pass MoeConfig backend override
LLM->>BackendResolver: resolve explicit MoE backend
BackendResolver->>CuteDslFusedMoE: validate NVFP4 SiTU eligibility
CuteDslFusedMoE->>SiTUKernel: pass SiTU beta parameters
SiTUKernel->>LLM: return fused MoE output
Merge Risk: 🔵 Low · up to Sequential SiTU beta configurations still lack verified regression coverage for kernel-cache separation. This is a bounded test-confidence risk that should be tracked before merge. 🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Inline comments:
In `@examples/kimi_k3/quick_start_kimi_k3.sbatch`:
- Line 43: Update the usage() function to include the accepted --moe-backend
option as [--moe-backend BACKEND], leaving the existing argument parsing
unchanged.
In `@tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`:
- Line 92: Update _canonicalize_situ_beta to return None only when situ_beta
equals the SITU_BETA_DISABLED sentinel, preserving explicit values such as 0.0
and -2.0. Add coverage for ActivationType.Swiglu confirming those values are
rejected by validation.
In
`@tensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_gather_grouped_gemm_act_fusion.py`:
- Around line 436-440: Update the SiTU beta validation in the constructor around
the existing situ_beta and situ_linear_beta check to reject any non-finite value
as well as zero or negative values, while preserving the current ValueError
behavior and message context. Add regression coverage in the Kimi SiTU MoE tests
for NaN, positive infinity, zero, and negative beta inputs.
In `@tensorrt_llm/_torch/models/modeling_kimi_linear.py`:
- Line 1141: Add a regression test in the Kimi K3 MoE runtime tests covering
explicit CUTEDSL selection when CUTEDSL is ineligible but CUTLASS is eligible.
Assert that KimiK3MoERuntime raises and includes the backend rejection trail,
rather than falling back to CUTLASS; keep existing allow-list and
configuration-preservation tests unchanged.
In `@tests/unittest/_torch/moe/test_kimi_k3_situ_moe.py`:
- Around line 1043-1044: Update the CUTEDSL test skip condition around
IS_CUTLASS_DSL_AVAILABLE to also require an SM100 or SM103 GPU, using the
existing device capability detection symbols in the test; skip before backend
resolution for all other architectures while preserving the current CuTe DSL
wheel check.
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examples/kimi_k3/eval_extra_llm_options_nvfp4_dep16.yamlexamples/kimi_k3/quick_start_kimi_k3.pyexamples/kimi_k3/quick_start_kimi_k3.sbatchtensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.pytensorrt_llm/_torch/cute_dsl_kernels/blackwell/blockscaled_contiguous_gather_grouped_gemm_act_fusion.pytensorrt_llm/_torch/models/modeling_kimi_linear.pytensorrt_llm/_torch/moe/fused_moe/fused_moe_cute_dsl.pytests/unittest/_torch/moe/test_kimi_k3_situ_moe.pytests/unittest/_torch/moe/test_moe_backend.py
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We rarely use the CUTLASS backend for kimi k3, so could we keep this test focused on CUTEDSL and remove the CUTLASS case to avoid spending CI resources on it? thanks
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Inline comments:
In `@tensorrt_llm/_torch/custom_ops/cute_dsl_custom_ops.py`:
- Around line 3460-3461: Add regression coverage in the SiTU MoE execution test
using the same CUTEDSL shape and tactic with two distinct beta pairs. Verify
each output against its corresponding SiTU reference and assert the outputs
differ, exercising beta-specific kernel-cache identity and preventing reuse
across soft-cap values.
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * Duplicate routing-input warnings demoted to debug across the TRTLLM-Gen MoE ops, except `fp4BlockScaleMoe.cpp` -- see below. * Drop the unused `<ATen/native/cuda/Resize.h>` includes from `moeOp.cpp` and `moeUtilOp.cpp`. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. `cpp/tensorrt_llm/thop/moe/fp4BlockScaleMoe.cpp` is deliberately left byte-identical to main. The EP-aware padded-token sizing this series carried for it (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. That change and the one-line log-level demote for the same file travel with NVIDIA#19251 rather than with SM107 enablement. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too.
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * Duplicate routing-input warnings demoted to debug across the TRTLLM-Gen MoE ops, except `fp4BlockScaleMoe.cpp` -- see below. * Drop the unused `<ATen/native/cuda/Resize.h>` includes from `moeOp.cpp` and `moeUtilOp.cpp`. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. `cpp/tensorrt_llm/thop/moe/fp4BlockScaleMoe.cpp` is deliberately left byte-identical to main. The EP-aware padded-token sizing this series carried for it (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. That change and the one-line log-level demote for the same file travel with NVIDIA#19251 rather than with SM107 enablement. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. * An NVFP4 SiTU MoE unit test, on the B200 L0 list. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. The NVFP4 SiTU MoE unit test that accompanied this work, its `l0_b200` entry and the de-duplication of the overlapping tactic-reachability case in `tests/unittest/_torch/thop/serial/test_moe.py` are not part of this series; this PR carries the production change only. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. The NVFP4 SiTU MoE unit test that accompanied this work, its `l0_b200` entry and the de-duplication of the overlapping tactic-reachability case in `tests/unittest/_torch/thop/serial/test_moe.py` are not part of this series; this PR carries the production change only. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. The NVFP4 SiTU MoE unit test that accompanied this work, its `l0_b200` entry and the de-duplication of the overlapping tactic-reachability case in `tests/unittest/_torch/thop/serial/test_moe.py` are not part of this series; this PR carries the production change only. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and rubin-advance serves Kimi K3 NVFP4 on CUTEDSL on SM107 (the DEP8 disagg GSM8K guard config uses it), so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and rubin-advance serves Kimi K3 NVFP4 on CUTEDSL on SM107 (the DEP8 disagg GSM8K guard config uses it), so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Port the MoE feature family from the Rubin development branch that main does not already carry: * PDL launch support in the SiTU Triton kernel (`_torch/modules/situ.py`), gated on `get_env_enable_pdl()` and SM >= 90. * `_Pointer.__add__` in `_torch/cute_dsl_kernels/rubin/moe/utils.py`, so a Rubin device pointer can be offset by an element count with the alignment narrowed to the real `gcd`. * A `moe_a2a_cft_release` hook on the NVLink one-sided teardown path: the C++ CFT logical endpoint is destroyed before the last Python reference to its MNNVL backing memory is dropped. * MegaMoE DeepGEMM rendezvous: trust `MASTER_ADDR`/`MASTER_PORT`/`RANK`/ `WORLD_SIZE` only when they actually describe this MPI world, so a disaggregated launcher's outer world cannot be adopted by an inner one. The NVFP4 SiTU MoE unit test that accompanied this work, its `l0_b200` entry and the de-duplication of the overlapping tactic-reachability case in `tests/unittest/_torch/thop/serial/test_moe.py` are not part of this series; this PR carries the production change only. Every `cpp/tensorrt_llm/thop/` translation unit this series used to touch is now left byte-identical to main. The EP-aware padded-token sizing carried for `fp4BlockScaleMoe.cpp` (`num_experts` -> `local_num_experts` for `getMaxPermutedPaddedCount` and `getMaxNumCtasInBatchDim`) is under separate review in NVIDIA#19251: `routingIndicesWarpKernel` in `RoutingLlama4.cu` counts tokens ungated by `isLocalExpert` and writes a global expert id as the CTA batch index, so the smaller allocation can be written out of bounds on the Llama4 routing path. The duplicate-routing-input log-level demote and the unused `<ATen/native/cuda/Resize.h>` include removals are unrelated to SM107 enablement and are dropped from this series; `th_common` is already built as C++20 on main, so those includes cost nothing but a line. Two things this series used to carry are now main's and are not restated here. `CuteDslFusedMoE.run_moe_nvfp4` already admits `ActivationType.SiTu` after NVIDIA#19003, so `fused_moe_cute_dsl.py` is left byte-identical to main. And the MegaMoE NVFP4 CuteDSL kernel tree that lived in `_torch/cute_dsl_kernels/mega_moe_nvfp4/` was deleted by PR NVIDIA#17956 and replaced with `_torch/cute_dsl_kernels/cutedsl_megamoe/`, which already carries the same SM107 work (renamed: `build_sm107_static_idesc_base` -> `build_static_idesc_base`, `Sm107MegaMoEKernel` -> `rubin/inference/mega/BlockScaledSwapAbMegaMoeKernel`, and so on). The `CuteDslFc12FusedMoE` backend and the Rubin fused-FC12 GEMM landed upstream too. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Oct 9, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Oct 9, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Oct 15, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
reasonsolo
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Oct 15, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
reasonsolo
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Oct 15, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Oct 16, 2026
NVIDIA#19003 enabled CuteDSL NVFP4 SiTU on SM100/SM103 and kept SM107 rejected pending end-to-end validation. The Rubin act-fusion kernel and op already carry the SiTU epilogue and soft-caps, and Kimi K3 NVFP4 has been served on CUTEDSL on SM107, so drop the SM107 rejection. Because Kimi K3 forbids silent degradation for CUTEDSL, the rejection made an explicit CUTEDSL request fail at resolution on SM107. Tests: a CPU-only can_implement check for SM100/SM103/SM107, and the NVFP4 SiTU kernel check now runs CUTEDSL on SM107 when Rubin CuTe DSL is present. Signed-off-by: Lizhi Zhou <1432185+reasonsolo@users.noreply.github.com>
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Description
Enable explicitly selected CUTEDSL routed experts for Kimi K3 NVFP4 on SM100/SM103. The Blackwell kernel already implements SiTU in the rebased main; this change enables it through the MoE capability declaration and K3 backend selection, forwards both soft-caps, and rejects an explicit CUTEDSL request that cannot be served instead of silently selecting CUTLASS.
The Blackwell custom op and fake schema use
Optional[float] = Nonedirectly. SiTU constants must be finite and positive. SM107 end-to-end SiTU integration remains gated; existing Rubin ops retain their separate legacy sentinel API.Review coverage
BACKEND_FAMILYand check exact agreement with the K3 allow-list.KimiK3MoERuntime/ resolver call chain with CUTEDSL ineligible and CUTLASS eligible; require an explicit rejection, with an allowed-degradation positive control.(4,25),(2,25),(4,10),(2,10)and verify distinct runner identities and numerical outputs.l0_b300.yml. Keep the numerical discriminator's CI selection focused on CUTEDSL as requested; retain the existing TRTLLM selector. Update the upstream Blackwell direct-op test to useNonefor absent SiTU parameters.Validation
Current PR head:
e04607744e7571a9817ce4bc0add0434591366f5. GPU validation ran at74a480e98701ba8423151f68503edd5e6db31e7b; the only subsequent change restores three example files to the base version. Implementation, unit tests, and CI selectors are unchanged. The DEP16 quickstart result below used the earlier example launcher with explicit backend selection. The branch was rebased onto63e64e5bdb447af0eb12b5b6ca6a185483131783.OCIAGA GB300/SM103, image
trtllm-ociaga-gb300-k3-base-nsys2025.5-20260916.sqsh;libtensorrt_llm.soSHA2563eac19a923ae4df65df65bd63d03a64d5716f5ce298424433738eeabc78b5eeb. Build job 802376 usedad95dd32a303; the GPU-validated candidate differs only in the CI selector YAML.GSM8K used
nvidia_kimi-k3-nvfp4/hf/hf-f8c5234_orig, 4 nodes × 4 GPUs in one NVLink segment, DEP16, batch size 8, KV fraction 0.35, 5-shot, all 1319/1319 questions, and a 256-token output limit. Nodes:nvl72d136-T[02,07-09].The same GSM8K run recorded both
CuteDslFusedMoE::run_moe_nvfp4andtrtllm::cute_dsl_nvfp4_gather_grouped_gemm_act_fusion_blackwellon every rank 0–15. These are runtime call-path records, emitted once per rank during warmup, rather than per-question kernel counts. There were notrtllm::fused_moe::gemm1records or resolver declines. The four soft-cap unit cases had relative L2 errors 0.164376 / 0.167295 / 0.165008 / 0.167400.These are local cluster validation results, not a claim that official PR GPU CI has passed. No performance improvement or backend ranking is claimed.
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