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dq_q2_0: keep the Q2_0 signed-zero fix on every HIP arch (#1474) - #1540
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…o1221#1474) The negative-scale-times-zero workaround was gated to gfx1012 on HIP < 7 and gfx1151 - the reports of the compiler fold so far. gfx1201 on ROCm 7.10 fails hip_q2_zero the same way (got 0x0000, expected 0x8000), so the arch list only ever chased the newest report. The workaround writes the scale's sign bit for code 1, which is value-identical on targets whose compiler never folds: keep it on every HIP build.
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Obsolete: the fix is in |
Niko1221
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Oct 17, 2026
…, #1474) The negative-scale-times-zero workaround was gated to an arch list (gfx1012 on HIP < 7, gfx1151, gfx1200/gfx1201 since 0ff45cf); the list only ever chased the newest report. The workaround writes the scale's sign bit for code 1, which is value-identical on targets whose compiler never folds: keep it on every HIP build. Ported from PR #1540 onto the tree that already carries the gfx1200/1201 entries; the comment text is adjusted. Co-authored-by: nekomario28 <206304251+nekomario28@users.noreply.github.com>
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Thanks nekomario28. The gfx1201 part was already in main (0ff45cf); we ported your generalisation to every HIP arch with you as co-author and hip_q2_zero passes on our R9700. |
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Summary
hip_q2_zerofails on gfx1201 (R9700) with ROCm 7.10: the half path folds a negative scale times +0 to +0, but thedq_q2_0workaround was gated to(__gfx1012__ && HIP_VERSION_MAJOR < 7) || __gfx1151__— the arch list only covers the reports seen so far, and gfx1201 on HIP 7 falls outside it.__HIPCC__. The workaround writes the scale's sign bit for code 1, which is value-identical on targets whose compiler never folds — this matches the reporter's proposed fix.Fixes #1474.
Test plan
amdclang++ -x hip -fsyntax-only --offload-arch=gfx1201onsrc/kernels/cuda/iq_kernels.cuwith the build's compat flags: cleanctest -R hip_q2_zeroon the reporter's R9700 / ROCm 7.10 build: expect PASS (128 signed-zero failures → 0)#if defined(__HIPCC__)only)