[Vop3p]

Results-only community report, no engine changes. Folder bench/results/2026-10-09-community-2x-rx-6900xt-0.1.41/ plus one row in bench/results/COMMUNITY.md (and the Notes block of that file moved below the table: 27 rows under it had no header and rendered as plain text).

Headline. Two 2020 RX 6900 XT 16 GB cards (a used pair is about US$550) decode IQ3_S at 82.3 tok/s at 32K on the layer split - the highest decode of any AMD row in the index, and among IQ3_S two-card entries second only to a pair of RTX 5090s. Prompt reads are 968 / 1,714 / 2,029 tok/s at 4K / 32K / 128K (63 s to the first token at 128K), also the highest of the AMD pairs in the index (2x RX 7900 GRE 1,583, 2x RX 9070 1,489, 2x RX 7900 XTX 1,451-1,561 at 32K). The decode gain over the same binary's default configuration is +19 / +20 / +11% and comes from configuration alone - --spec 3 --spec-min-p 0.7 --pipeline-windows 2, no engine change, so any card can try it; each of the two knobs alone had measured neutral or worse here, only the pair works. A real agent workload on the production server (93K context, a 14,821-token reply) decoded at 97.1 tok/s, above the synthetic numbers.

Same machine as the 2026-10-05 and 2026-10-06 reports (gfx1030, PCIe 4.0 x8 each; Ryzen 5 5600X; 128 GB; ROCm 10.0). IQ3_S at 131K, eleven arms (one card, layer split, expert helper x stock / switches / PRs, plus the decode-window arm), two runs per length, no vision encoder, zero stalls. The split arms:

arm	prompt tok/s 4K / 32K / 128K	decode tok/s
stock 0.1.41 (fb58e0db)	464 / 767 / -	62.6 / 65.0 / -
stock + STRATA_HIP_ADAPT_KERNEL_COPY=1	461 / 767 / 869	61.5 / 65.1 / 60.8
+ STRATA_HIP_PROMPT_F16=1 STRATA_SH_STREAM=1	832 / 1,619 / 1,823	69.2 / 74.6 / 67.5
+ #1149 #1151 #1167, rocBLAS solution cache, RDNA2 MMQ patches in ggml	968 / 1,714 / 2,029	64.7 / 68.8 / 68.3
the same with --spec 3 --spec-min-p 0.7 --pipeline-windows 2	968 / 1,707 / 2,041	77.2 / 82.3 / 75.7

One card (PCI 0f, GFXOFF default), medians of two runs:

	4K prompt	4K decode	32K prompt	32K decode	128K prompt	128K decode
stock	473	45.6	502	48.0	486	46.6
switches	850	49.0	1,102	51.6	1,027	49.3
PRs + ggml	976	49.0	1,174	50.9	1,147	49.8

One card with the other as expert helper (--expert-cache-device1 auto --remote-expert-opt, STRATA_HIP_ADAPT_KERNEL_COPY=1):

	4K prompt	4K decode	32K prompt	32K decode	128K prompt	128K decode
stock + kernel-copy	477	67.7	503	66.5	487	65.2
switches + kernel-copy	859	69.0	1,103	74.9	1,028	70.7
PRs + ggml + kernel-copy	986	72.5	1,173	75.2	1,147	75.1

A 16 GB card alone holds about 4,500 expert slots (83% hit rate), so one-card decode is 46-52 whatever the tree; the helper mode decodes 65-75 at one card's prompt speed. Against 0.1.40.1 the one-card pattern repeats the split's: stock +3-6%, switches +5-13%, PRs +1-2%. Full tables with ranges, TTFT and totals are in the README.

Where this sits among the index's AMD rows (32K, IQ3_S unless noted):

	prompt tok/s	decode tok/s
2x RX 6900 XT 16 GB, this report	1,714	82.3
2x RX 7900 GRE 16 GB (2026-10-06 folder, --pipeline-windows 2)	1,583	69.3
2x RX 9070 / 9070 XT 16 GB (#1565, 0.1.40.2)	1,489	64.5
2x RX 7900 XTX 24 GB (#1386, 0.1.40)	1,451-1,561	56.6
RX 7900 XTX 24 GB, one card (hipBLASLt table)	1,535-1,687	61-62

What is new against the 0.1.40.1 report from this box:

• Stock 0.1.41 reads prompts 4-6% faster than stock 0.1.40.1 on the split; with the two switches 5-12% faster. The pull requests land where they did (968 / 1,685 / 2,003 then).
• STRATA_HIP_ADAPT_KERNEL_COPY=1 costs nothing measurable and the stock split read its 128K prompts at the GFXOFF default without the HIP gfx1030, 2x RX 6900 XT: verify hangs after a long prompt when MMQ prompt path, adaptive expert swaps and SDMA meet (any one off avoids it) #884 stall; the 0.1.40.1 report had to disable GFXOFF through debugfs for that.
• The split point moves 32K decode by about 8% (0-24/25-47 without the vision encoder vs 0-26/27-47 with it, same binary); written up as an observation, not swept.
• --pipeline-windows 2 makes greedy output differ between server starts on this machine; the README says so.

Per-arm folders have config.json, summary.json, results.json and BUILD.txt; the engine logs and one-second telemetry are in the companion repository (https://github.com/Vop3p/dual-6900xt-flash-next-tuning, bench/results/e388/), which also holds the step-by-step tuning history behind the "PRs" arm (274 / 23.7 tok/s on llama.cpp three weeks ago) and the six llama.cpp patches.

Developed with an AI coding assistant; every number above was measured on 2x RX 6900 XT (gfx1030, PCIe 4.0 x8 each) / Ryzen 5 5600X, ROCm 10.0.

[Vop3p]

One note for other AMD pairs on ROCm: nothing in the "PRs" arm is specific to the RX 6900 XT. The two shipped switches, pinning the BLAS solution per shape instead of trusting the start-up heuristic, the SIMT block scorer, STRATA_HIP_ADAPT_KERNEL_COPY=1 against #884, and a hand-picked layer_split should carry over to any two-card AMD box.

A data point: #1565's 2x RX 9070 on stock 0.1.40.2 with the hipBLASLt table reads 842 / 1,489 / 1,916 tok/s at 4K / 32K / 128K, which is where our stock-plus-switches arm lands (832 / 1,619 / 1,823). The step from there to 968 / 1,714 / 2,029 is the three open PRs, the per-device solution cache and the MMQ patches. gfx1201 has WMMA, so the FP16 route has more headroom there than on gfx1030; that the newer pair currently ties the older one says the gfx1201 path has not had the same treatment yet, not that the cards are slower. The A/B harness in the companion repository is meant to make that reproducible on other AMD boxes.

[Niko1221]

Thank you, in v0.1.42 with your commits squashed into one, and the 0.1.40.1 row in bench/results/COMMUNITY.md now carries the numbers you added.