boards/qemu-intel64: add citest configuration - #20030
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CI container uses old QEMU version that doens't support x2APIC, so we need this PR to run it #20044 |
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CI/NTFC testing config for intel64 Signed-off-by: raiden00pl <raiden00@railab.me>
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intel64_oneshot_start() takes g_oneshot_spin and then, if the timer is already running, calls intel64_oneshot_cancel(), which takes the same spinlock again. Spinlocks are not recursive, so the CPU spins forever on its own lock while holding the critical section; the HPET timer ISR on another CPU then blocks on g_cpu_irqlock and the system hangs. This is hit as soon as the tickless scheduler re-arms a running HPET oneshot timer under SMP (ostest task_restart, LTP aio tests). Stop the running timer inline instead of calling cancel: disable the interrupt, detach the ISR so up_enable_irq() does not assert on a busy IRQ, and clear the running flag. The ISR, comparator and interrupt enable are reprogrammed by the rest of the function anyway. Assisted-by: Claude Code Signed-off-by: raiden00pl <raiden00@railab.me>
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Summary
CI/NTFC testing config for intel64
Impact
CI tests for intel64
Testing
CI