[SME] Add support for inserting processor state annotations - #16761
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Execution of SME instructions requires the processor be in a certain state. This functionality can be can be controlled using LLVM function level annotations such as "aarch64_pstate_sm_enabled" or "aarch64_pstate_za_new" (see arm_utils.py for more information). This commit exposes this functionality for AArch64 schedules where SME intrinsics will be called. The attributes are intended to be added at the block-level around the compute definition. They are prepended with "pragma" to ensure they remain in the lowering. In order to detect these attributes and convert them to the relevant LLVM function attributes, a new AArch64 LLVM codegen backend is added. This backend extends the functionality of `codegen_llvm` for AArch64 specific compilation. Tests to check these attributes propagate correctly have been added. Change-Id: I5b848afdeedd395de4650bf06720ea57e50ebd78
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…6761) Execution of SME instructions requires the processor be in a certain state. This functionality can be can be controlled using LLVM function level annotations such as "aarch64_pstate_sm_enabled" or "aarch64_pstate_za_new" (see arm_utils.py for more information). This commit exposes this functionality for AArch64 schedules where SME intrinsics will be called. The attributes are intended to be added at the block-level around the compute definition. They are prepended with "pragma" to ensure they remain in the lowering. In order to detect these attributes and convert them to the relevant LLVM function attributes, a new AArch64 LLVM codegen backend is added. This backend extends the functionality of `codegen_llvm` for AArch64 specific compilation. Tests to check these attributes propagate correctly have been added.
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Execution of SME instructions requires the processor be in a certain state. This functionality can be can be controlled using LLVM function level annotations such as "aarch64_pstate_sm_enabled" or "aarch64_pstate_za_new" (see arm_utils.py for more information).
This commit exposes this functionality for AArch64 schedules where SME intrinsics will be called. The attributes are intended to be added at the block-level around the compute definition. They are prepended with "pragma" to ensure they remain in the lowering.
In order to detect these attributes and convert them to the relevant LLVM function attributes, a new AArch64 LLVM codegen backend is added. This backend extends the functionality of
codegen_llvmfor AArch64 specific compilation.Tests to check these attributes propagate correctly have been added.