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Arm64-SVE: Implement Vector<T> HIR with SVE - #133422

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snickolls-arm:sve-hir

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@snickolls-arm

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Implement the Vector<T> API surface and various internal HIR transforms using SVE intrinsics, when InstructionSet_VectorT is enabled.

Implement the Vector<T> API surface and various internal HIR transforms
using SVE intrinsics, when InstructionSet_VectorT is enabled.
@github-actions github-actions Bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Sep 8, 2026
@dotnet-policy-service dotnet-policy-service Bot added the community-contribution Indicates that the PR has been added by a community member label Sep 8, 2026
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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@dotnet/arm64-contrib @tannergooding

Please could I have a review for this patch? It fills out most of the API surface for Vector<T> with SVE intrinsic implementations.

N.B. I have left some of the more involved algorithms blank (such as recently added geometric/harmonic sequences) to improve on in future. These two in particular don't have a software fallback for Vector<T> with Vector<byte>.Count > 16, so they will assert on hardware with larger vector lengths. I think it will be best to provide to provide an accelerated implementation so we can try to make use of predication.

@SwapnilGaikwad

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cc: @dhartglassMSFT

msk = gtNewSimdIsNegativeNode(retType, msk, simdBaseType, simdSize);
retNode = gtNewSimdCndSelNode(retType, msk, ovf, tmpDup2, simdBaseType, simdSize);
}
#elif defined(TARGET_ARM64)

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Is this ARM64 ifdef needed here? The previous ARM64 ifdef line ~3087 seems to do the same thing.

Similar question for SubtractSaturate below

@jkotas jkotas added arm-sve Work related to arm64 SVE/SVE2 support arch-arm64 labels Oct 9, 2026
assert((totalSize <= 64) && (totalSize <= MaxStructSize));

#if defined(TARGET_ARM64)
// The VM returns the concrete runtime contents of the field, but a scalable GT_CNS_VEC

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do we want a TODO to look for basic sequences/constants, or do you think thats not worth it

//
// For equality, we test whether this sequence returned zero.
LIR::Use originalUse;
BlockRange().TryGetUse(node, &originalUse);

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TryGetUse can fail to find a use

GenTree* vectorLength = evalVectorCount(vectorTHandle, simdBaseType);

GenTree* op2Clone = nullptr;
op2 = impCloneExpr(op2, &op2Clone, CHECK_SPILL_ALL, nullptr DEBUGARG("Clone index for Vector<T> bounds check"));

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op2 may have side effects, and impCloneExpr may force a spill to a temp first. This can mess up evaluation order. The "if (rangeCheckNeeded)" along the non-scalable path below in this routine also considers that.


op2 = gtNewOperNode(GT_COMMA, op2->TypeGet(), boundsCheck, op2);

if (op2->IsIntegralConst())

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Does this check ever succeed? (IsIntegralConst())

Since op2 is a GT_COMMA here

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4 participants