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JIT: Use smaller xarch mov encoding when long fits into int #135182

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JIT: Use smaller xarch mov encoding when long fits into int #135182

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d8fe020
* Use 'MOV r/m64, imm32' over 'MOV r64, imm64' when the long fits int…
BoyBaykiller Oct 4, 2026
e60c48c
* add special path for isSignExtendingMov
BoyBaykiller Oct 4, 2026
d22835f
* format
BoyBaykiller Oct 4, 2026
559145f
* add missing AddX86PrefixIfNeededAndNotPresent for new APX regs
BoyBaykiller Oct 4, 2026
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32 changes: 29 additions & 3 deletions src/coreclr/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7175,7 +7175,7 @@ void emitter::emitIns_R_I(instruction ins,
#ifdef TARGET_AMD64
// mov reg, imm64 is the only opcode which takes a full 8 byte immediate
// all other opcodes take a sign-extended 4-byte immediate
noway_assert(size < EA_8BYTE || ins == INS_mov || ((int)val == val && !EA_IS_CNS_RELOC(attr)));
noway_assert(size < EA_8BYTE || ins == INS_mov || (FitsIn<int32_t>(val) && !EA_IS_CNS_RELOC(attr)));
#endif

UNATIVE_OFFSET sz;
Expand Down Expand Up @@ -7206,7 +7206,15 @@ void emitter::emitIns_R_I(instruction ins,

if (size > EA_4BYTE)
{
sz = 9; // Really it is 10, but we'll add one more later
// Really it is 7 and 10, but we'll add one more later
if (FitsIn<int32_t>(val) && !EA_IS_CNS_RELOC(attr))
{
sz = 6; // Sign-extended 4-byte immediate
}
else
{
sz = 9; // Standard 8-byte immediate
}
break;
}
#endif // TARGET_AMD64
Expand Down Expand Up @@ -16956,6 +16964,24 @@ BYTE* emitter::emitOutputRI(BYTE* dst, instrDesc* id)
}

// The 'mov' opcode is special
bool isSignExtendingMov = (size == EA_8BYTE) && FitsIn<int32_t>(val) && !id->idIsCnsReloc();
if ((ins == INS_mov) && isSignExtendingMov)
Comment on lines +16967 to +16968
{
// This is INS_mov and will not take VEX prefix
assert(!TakesVexPrefix(ins));

// Move imm32 sign extended to 64-bit register: mov r/m64, imm32
code = insCodeMI(ins) | 0x1; // C7
code = AddX86PrefixIfNeededAndNotPresent(id, code, size);
code = insEncodeMIreg(id, reg, size, code);
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code = AddRexWPrefix(id, code);

dst += emitOutputRexOrSimdPrefixIfNeeded(ins, dst, code);
dst += emitOutputWord(dst, code);
dst += emitOutputLong(dst, val);

goto DONE;
}
if (ins == INS_mov)
{
code = insCodeACC(ins);
Expand Down Expand Up @@ -17287,7 +17313,7 @@ BYTE* emitter::emitOutputIV(BYTE* dst, instrDesc* id)

#ifdef TARGET_AMD64
// all these opcodes take a sign-extended 4-byte immediate, max
noway_assert(size < EA_8BYTE || ((int)val == val && !id->idIsCnsReloc()));
noway_assert(size < EA_8BYTE || (FitsIn<int32_t>(val) && !id->idIsCnsReloc()));
#endif

if (id->idIsCnsReloc())
Expand Down
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