[Code Health] host_build_graph: chip-swimlane level 4 (orch phases) is a no-op; device allocates+flushes a dead orch-phase pool #1802

Category

Dead Code / Unused Dependencies

Component

Orchestration

Description

On host_build_graph (hbg), --enable-chip-swimlane 4 (orchestrator phases) collects no orchestrator records — it behaves identically to level 3 plus an empty aicpu_orchestrator_phases[] array. Two problems:

1. Misleading level. Level 4 is advertised (--enable-chip-swimlane help, profiling_levels.md) but yields nothing on hbg, because the orchestrator runs on the host, where chip_swimlane_aicpu_record_orch_phase is a weak no-op (the strong symbol lives only in the AICPU .so, which never orchestrates in hbg).
2. Dead code on the device. The scheduler cold path still initializes an orch-phase pool (orch_phase_threads = 1) and flushes it in on_orchestration_done, even though it is always empty in hbg.

Levels 1–3 (AICore timing / AICPU dispatch-finish / scheduler phases) work correctly on hbg — this is only about level 4. The swimlane_converter.py already tolerates an empty orch array (no orch lane is emitted), so there is no crash, just dead work and a level that promises data it never delivers.

This is the host-orch class of hbg DFX gaps tracked under #1706; the host-side orchestrator-phase collection overlaps with the host swimlane L3/L4 request in #1708.

Location

- Weak no-op record fn (host build): `src/a2a3/runtime/host_build_graph/runtime/orchestrator_core/pto_orchestrator.cpp:134,146`
- Dead orch-phase pool init: `src/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cpp:840`
- Dead orch-phase pool flush: `src/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_cold_path.cpp:1060`

Proposed Fix

Two options (pick per the direction chosen for #1708):

• Honest-minimal: cap hbg at level 3 (reject/clamp level 4 for hbg with a clear message) and delete the device-side empty orch-phase pool init + flush. Smallest, removes the dead code and the misleading level.
• Feature-complete: implement host-side orchestrator-phase collection (the host orchestrator's per-task submit timing) feeding the existing chip_swimlane_records.json orch lane, so level 4 delivers real host-orch timing. Larger; aligns with [Feature] Host swimlane (L3/L4) — the missing third DFX timeline #1708.

Priority

Medium (minor risk, should fix in next few releases)