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Fix: close level-4 chip swimlane follow-ups - #1859
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Included review availability: Your plan includes up to 1 review per rolling hour; 0 remain after this review. 📝 WalkthroughWalkthroughLevel-4 chip-swimlane profiling now separates host-build-graph orchestrator phases from TMR AICPU phases. Runtime capture includes clock correlation and invalid-interval reporting. Converters, validators, documentation, unit tests, and optional simulation smoke tests support the new output. ChangesHost orchestrator swimlane support
Estimated code review effort: 4 (Complex) | ~45 minutes Merge Risk: 🟡 Moderate · up to The PR changes profiling validation, host-capture error reporting, and exported lane-schema semantics, but current-head risks remain: stale output could produce a false-positive smoke result, capture failures could be misreported, and consumers could misinterpret HBG lane indices. Merge should wait for these issues to be fixed or explicitly accepted by the owners. Sequence Diagram(s)sequenceDiagram
participant HostBuildGraphTest
participant HostBuildGraphRuntime
participant ChipSwimlaneCollector
participant SwimlaneArtifact
participant CaptureValidator
HostBuildGraphTest->>HostBuildGraphRuntime: run record_then_replay_2d
HostBuildGraphRuntime->>ChipSwimlaneCollector: capture host orchestrator phases
ChipSwimlaneCollector->>SwimlaneArtifact: export phases and timeline metadata
HostBuildGraphTest->>CaptureValidator: validate artifact after the test
CaptureValidator->>SwimlaneArtifact: check records, anchors, alignment, and reader output
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🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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Actionable comments posted: 3
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Inline comments:
In `@docs/dfx/chip-swimlane-profiling.md`:
- Around line 232-237: Update the heading describing the phase arrays to
“Per-lane arrays,” and clarify that host_orchestrator_phases uses a single host
lane rather than scheduler-thread indexing. Keep the existing scheduler and TMR
lane descriptions unchanged.
In `@src/common/platform/shared/host/chip_swimlane_collector.cpp`:
- Around line 935-938: Ensure the later RecordAllocationFailed assignment in the
host-capture collection path only occurs when host_capture_error_ is
HostCaptureError::None, preserving an earlier InvalidRecordInterval (or any
first error) in the exported metadata. Update the push_back failure handling
near host_capture_dropped_records_ without changing the existing first-error
behavior.
In `@tests/st/a2a3/host_build_graph/graph_execution/test_graph_execution.py`:
- Line 90: Preserve subsecond artifact-boundary precision by passing time.time()
directly instead of converting it with int() in the run_marker setup. Apply this
change at tests/st/a2a3/host_build_graph/graph_execution/test_graph_execution.py
lines 90-90 and
tests/st/a5/host_build_graph/graph_execution/test_graph_execution.py lines
89-89; both sites require the same direct timestamp change.
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📒 Files selected for processing (19)
.github/workflows/_st-sim-a2a3.yml.github/workflows/_st-sim-a5.ymldocs/dfx/chip-swimlane-profiling.mdsimpler_setup/tools/README.mdsimpler_setup/tools/swimlane_converter.pysrc/a2a3/runtime/host_build_graph/host/runtime_maker.cppsrc/a5/runtime/host_build_graph/host/runtime_maker.cppsrc/common/platform/include/host/chip_swimlane_collector.hsrc/common/platform/include/host/clock_correlation.hsrc/common/platform/onboard/host/clock_correlation.cppsrc/common/platform/onboard/host/device_runner_base.cppsrc/common/platform/shared/host/chip_swimlane_collector.cppsrc/common/platform/sim/host/device_runner_base.cpptests/st/a2a3/host_build_graph/graph_execution/test_graph_execution.pytests/st/a2a3/tensormap_and_ringbuffer/dfx/chip_swimlane/_swimlane_validate.pytests/st/a5/host_build_graph/graph_execution/test_graph_execution.pytests/st/a5/tensormap_and_ringbuffer/dfx/chip_swimlane/_swimlane_validate.pytests/st/chip_swimlane_validation.pytests/ut/py/test_swimlane_converter.py
💤 Files with no reviewable changes (1)
- src/common/platform/include/host/clock_correlation.h
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- Add A2/A3 and A5 simulation coverage for HBG host and TMR AICPU orchestrator phases. - Correct host capture drop/error accounting and make level gates forward-compatible. - Keep HBG and TMR phase streams source-accurate in reader output. - Document lane schemas, clock alignment, export semantics, and validation results. - Reject stale simulation artifacts at subsecond boundaries and keep HBG post-validation simulation-only.
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Summary
sim_syscntprovider contract.host_orchestrator_phaseswhile retainingaicpu_orchestrator_phasesfor TMR, including updated converter consumers and regression tests.Follow-up to #1846.
Testing
pip install --no-build-isolation -e .pytest tests/ut/py/test_clock_correlation.py tests/ut/py/test_swimlane_converter.py tests/ut/py/test_scene_level_selection.py -q— 41 passed