Remove documentation that describes things that no longer exist

docs/buffer-abi.md

@@ -250,7 +250,7 @@ A `Tensor` on the wire is materialized differently by each consumer:
 
 | Consumer | What it does |
 | -------- | ------------ |
-| **Chip leaf (L2 runtime)** | Materialize each one to a `ChipTensor` (map-once, keyed by identity), including **strided** views; hand the POD blob to `run_from_blob`. |
+| **Chip leaf (L2 runtime)** | Decode the POD blob with `read_args_from_blob`, then materialize each one to a `ChipTensor` (map-once, keyed by canonical identity) via `ImportRegistry.materialize_args`, including **strided** views, and submit with `_submit_chip_run_materialized`. |
 | **Python sub-worker** (compute) | Map each one into a `MappedArg`; the callable computes with `torch.frombuffer(arg.buffer, ...)`. No `ChipTensor`. |
 | **Nested L4→L3 orch** (forwarding) | **Re-export** each backing to a descriptor `H'` that keeps the source's canonical identity — no pass-through, no map on the forwarding hop. |
 

src/a2a3/runtime/host_build_graph/docs/RUNTIME_LOGIC.md

@@ -124,8 +124,9 @@ scalar `rt_orchestration_done` publishes into the runtime header.
 
 **Why the scheduler state is device-written.** `SchedulerState` holds no
 per-run content: `sm_header` and the task-header pointer derive from a pooled SM base,
-queue capacities are compile-time constants, hbg never advances
-`last_task_alive`, and it has no host-side entry point at all. So the host would
+queue capacities are compile-time constants, polling reserves no wiring or
+dependency pool (readiness comes from the task table's `completion_flags`, which
+the task header owns), and it has no host-side entry point at all. So the host would
 only be writing an initialization pattern — 203,392 bytes
 of it, dominated by `AsyncWaitList::entries` — for the device to receive and never
 read. `RuntimeContext` therefore holds a *pointer* to it, wired from

src/a2a3/runtime/host_build_graph/docs/SCALAR_DATA_ACCESS.md

@@ -70,7 +70,9 @@ it derives for itself, from a heap block whose prior contents it never reads.
 
 Before a wait slot is used, the runtime verifies:
 
-- the task ID is valid and carries ring 0, the only ring HBG places tasks on;
+- the task ID is valid and lies in the `RING` id space — a `GRAPH_NODE` id packs
+  its outer task and node index into the low bits, so it indexes no task table
+  slot (see `src/common/host_build_graph/task_id_encoding.h`);
 - the task table slot that ID indexes has a bound task descriptor; and
 - the descriptor's full task ID matches the tensor's owner/producer ID.
 

src/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler.h

@@ -689,11 +689,11 @@ struct SchedulerState {
     EarlyDispatchDoorbell early_dispatch_doorbell_table[EARLY_DISPATCH_CORE_MASK_WORDS * 64]{};
 
     // Cross-thread early-dispatch work queues, one ChipReadyQueue MPMC instance per
-    // resource shape (AIC/AIV/MIX) — arena-backed, reserved/wired in pto_runtime2_init
-    // alongside the per-shape ready queues, and indexed the same way. A candidate is
-    // pushed to the queue for its own shape (active_mask.to_shape()) so the drain can
-    // pop per shape and size the pop to that shape's free cores, exactly as normal
-    // dispatch pops ready_queues[shape].
+    // resource shape (AIC/AIV/MIX) — arena-backed, reserved and wired by
+    // SchedulerState::init_data_from_layout alongside the per-shape ready queues, and
+    // indexed the same way. A candidate is pushed to the queue for its own shape
+    // (active_mask.to_shape()) so the drain can pop per shape and size the pop to that
+    // shape's free cores, exactly as normal dispatch pops ready_queues[shape].
     //
     // A consumer's SPMD blocks span cores owned by several AICPU threads, but only a
     // thread RUNNING the consumer's producer discovers it (via the producer's

src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler.h

@@ -735,11 +735,11 @@ struct SchedulerState {
     EarlyDispatchDoorbell early_dispatch_doorbell_table[EARLY_DISPATCH_CORE_MASK_WORDS * 64]{};
 
     // Cross-thread early-dispatch work queues, one ChipReadyQueue MPMC instance per
-    // resource shape (AIC/AIV/MIX) — arena-backed, reserved/wired in pto_runtime2_init
-    // alongside the per-shape ready queues, and indexed the same way. A candidate is
-    // pushed to the queue for its own shape (active_mask.to_shape()) so the drain can
-    // pop per shape and size the pop to that shape's free cores, exactly as normal
-    // dispatch pops ready_queues[shape].
+    // resource shape (AIC/AIV/MIX) — arena-backed, reserved and wired by
+    // SchedulerState::init_data_from_layout alongside the per-shape ready queues, and
+    // indexed the same way. A candidate is pushed to the queue for its own shape
+    // (active_mask.to_shape()) so the drain can pop per shape and size the pop to that
+    // shape's free cores, exactly as normal dispatch pops ready_queues[shape].
     //
     // A consumer's SPMD blocks span cores owned by several AICPU threads, but only a
     // thread RUNNING the consumer's producer discovers it (via the producer's

src/a5/runtime/host_build_graph/docs/RUNTIME_LOGIC.md

@@ -124,8 +124,9 @@ scalar `rt_orchestration_done` publishes into the runtime header.
 
 **Why the scheduler state is device-written.** `SchedulerState` holds no
 per-run content: `sm_header` and the task-header pointer derive from a pooled SM base,
-queue capacities are compile-time constants, hbg never advances
-`last_task_alive`, and it has no host-side entry point at all. So the host would
+queue capacities are compile-time constants, polling reserves no wiring or
+dependency pool (readiness comes from the task table's `completion_flags`, which
+the task header owns), and it has no host-side entry point at all. So the host would
 only be writing an initialization pattern — 203,392 bytes
 of it, dominated by `AsyncWaitList::entries` — for the device to receive and never
 read. `RuntimeContext` therefore holds a *pointer* to it, wired from

src/a5/runtime/host_build_graph/docs/SCALAR_DATA_ACCESS.md

@@ -70,7 +70,9 @@ it derives for itself, from a heap block whose prior contents it never reads.
 
 Before a wait slot is used, the runtime verifies:
 
-- the task ID is valid and carries ring 0, the only ring HBG places tasks on;
+- the task ID is valid and lies in the `RING` id space — a `GRAPH_NODE` id packs
+  its outer task and node index into the low bits, so it indexes no task table
+  slot (see `src/common/host_build_graph/task_id_encoding.h`);
 - the task table slot that ID indexes has a bound task descriptor; and
 - the descriptor's full task ID matches the tensor's owner/producer ID.
 

src/a5/runtime/host_build_graph/runtime/scheduler/scheduler.h

@@ -689,11 +689,11 @@ struct SchedulerState {
     EarlyDispatchDoorbell early_dispatch_doorbell_table[EARLY_DISPATCH_CORE_MASK_WORDS * 64]{};
 
     // Cross-thread early-dispatch work queues, one ChipReadyQueue MPMC instance per
-    // resource shape (AIC/AIV/MIX) — arena-backed, reserved/wired in pto_runtime2_init
-    // alongside the per-shape ready queues, and indexed the same way. A candidate is
-    // pushed to the queue for its own shape (active_mask.to_shape()) so the drain can
-    // pop per shape and size the pop to that shape's free cores, exactly as normal
-    // dispatch pops ready_queues[shape].
+    // resource shape (AIC/AIV/MIX) — arena-backed, reserved and wired by
+    // SchedulerState::init_data_from_layout alongside the per-shape ready queues, and
+    // indexed the same way. A candidate is pushed to the queue for its own shape
+    // (active_mask.to_shape()) so the drain can pop per shape and size the pop to that
+    // shape's free cores, exactly as normal dispatch pops ready_queues[shape].
     //
     // A consumer's SPMD blocks span cores owned by several AICPU threads, but only a
     // thread RUNNING the consumer's producer discovers it (via the producer's