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Refactor: rename A5 HBG Resolver to Scheduler - #2119
ChaoZheng109 merged 1 commit into
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📝 WalkthroughWalkthroughThe change renames A5 resolver terminology to scheduler terminology, updates scheduler worker contracts and APIs, and raises profiling timestamp gates to ChangesScheduler profiling alignment
A5 scheduler runtime
Scheduler terminology test updates
Estimated code review effort: 3 (Moderate) | ~20 minutes Merge Risk: 🔵 Low · up to Shorter AICore profiling batches can include records from a previous batch, making exported diagnostics misleading. Correct the buffer reset or flush count before relying on this output. Poem
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 15.13% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 119 functions across 31 files. (6 skipped: 6 unsupported.)
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Inline comments:
In `@src/common/platform/shared/aicpu/chip_swimlane_collector_aicpu.cpp`:
- Around line 731-733: Update aicore_rotate() to clear recycled buffer records
before reuse, or ensure AICORE_TIMING publishes the exact live record count
instead of the full capacity; preserve copy_aicore_buffer() filtering and add a
regression test verifying shorter batches do not export stale tail records.
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📒 Files selected for processing (37)
docs/dfx/profiling-config-naming.mdsimpler_setup/tools/swimlane_converter.pysrc/a2a3/runtime/host_build_graph/docs/profiling_levels.mdsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_completion.cppsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_context.hsrc/a2a3/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/docs/profiling_levels.mdsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_completion.cppsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/host_build_graph/aicore/aicore_executor.cppsrc/a5/runtime/host_build_graph/aicpu/aicore_lifecycle.cppsrc/a5/runtime/host_build_graph/aicpu/aicpu_executor.cppsrc/a5/runtime/host_build_graph/docs/profiling_levels.mdsrc/a5/runtime/host_build_graph/host/runtime_maker.cppsrc/a5/runtime/host_build_graph/runtime/dispatch_payload.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_completion.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_completion.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_context.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_ready.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_topology.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_types.hsrc/a5/runtime/tensormap_and_ringbuffer/docs/profiling_levels.mdsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_completion.cppsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_context.hsrc/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cppsrc/common/host_build_graph/docs/GRAPH_EXECUTION.mdsrc/common/platform/include/aicpu/chip_swimlane_collector_aicpu.hsrc/common/platform/include/common/chip_swimlane_profiling.hsrc/common/platform/include/host/chip_swimlane_collector.hsrc/common/platform/shared/aicpu/chip_swimlane_collector_aicpu.cppsrc/common/platform/shared/host/chip_swimlane_collector.cpptests/st/a5/host_build_graph/empty_lifecycle/test_empty_lifecycle.pytests/ut/cpp/a5/test_hbg_scheduler_dispatch.cpptests/ut/cpp/a5/test_hbg_scheduler_ready.cpp
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ChaoZheng109
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The A5 HBG Resolver → Scheduler rename itself looks good: field order and types are preserved across the shared-memory boundary, the sizeof/alignof static_asserts are intact, the dispatch / ready-directory / deferred-AIV logic is unchanged line-for-line, grep -i resolver src/a5 is now empty, and CI is green including ut-a5 and st-onboard-a5. No objection to the code part.
Four comments below, two of which are about changes that fall outside the stated scope of this PR and are, I believe, incorrect:
src/common/host_build_graph/docs/GRAPH_EXECUTION.md— an arch-neutral common doc now claims an A5-specific mechanism, contradicting the very next paragraph.- Three
profiling_levels.mdfiles now name a JSON key that does not exist anywhere in the repo. AICPU_TIMING→SCHEDULER_TASK_TIMINGleaves a half-migrated surface, and the canonical user-facing DFX doc was not updated with the other four.- Two renamed constants and one function now stutter (
SCHEDULER_SCHEDULER_CAPACITY).
Leaving this as a comment rather than a blocking review — but 1 and 2 are factual errors rather than style, so they are worth fixing before merge.
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Use Scheduler consistently for the A5 HBG AICore worker role. Rename its state, helpers, constants, and tests without changing behavior. Name chip-swimlane task and schedule timing levels by role while preserving their numeric values and on-disk schema.
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@ChaoZheng109 Addressed all requested review points:
The separate recycled-buffer lifecycle observation was intentionally left unchanged because it predates and is outside this rename PR. |
Why
The A5
host_build_graphAICore worker performs scheduling, but its internal state and documentation still called that role a Resolver. Using two names for the same role obscures ownership in the dispatch, ready-queue, completion, and profiling paths.What changed
AICORE_TIMING/AICPU_TIMINGtoTASK_TIMING/SCHEDULE_TIMING; keepSCHED_PHASESandORCH_PHASESunchanged.Reviewer guide
Testing
python -m pip install --no-build-isolation -e .