[top-i2c,dv] Added chip level I2C Device TX_RX test#633
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engdoreis
left a comment
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I left a suggestion, otherwise it LGTM.
| VOLATILE_WRITE(i2c->txdata, txdata); | ||
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| void i2c_clear_cmd_complete(i2c_t i2c) |
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I suggest making a function to clear interrupts that take the interrupt as argument like uart:
mocha/sw/device/lib/hal/uart.c
Line 36 in 3b3b9e2
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Do you mean something like that:
void i2c_clear_intr_state(i2c_t i2c, uint32_t state)
{
VOLATILE_WRITE(i2c->intr_state, state);
}
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Yes, but 'state' would be an enum with the interrupts. It should also accept more then one interrupt per call.
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| @@ -37,23 +69,42 @@ function int unsigned top_chip_dv_i2c_tx_rx_vseq::round_up_divide(int unsigned a | |||
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| function void top_chip_dv_i2c_tx_rx_vseq::configure_agent_timing(); | |||
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I think these changes also have an impact on top_chip_dv_i2c_host_tx_rx_vseq. Isn't it an issue?
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I don't think that host_tx_rx_test gets affected. I've took these calculations from i2c_base_vseq function get_timing_values(). They look sensible to reason.
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Oh, sorry. I think I didn't answer this question well. These parameters are used to add delays which should depend on the speed of the I2C bus and not on host / device part. So, whatever the speed is just calculate the timing parameter the same way
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A reviewer on lowRISC#633 commented about inconsistency in the naming of tBUF timing parameter accross different places. That made me look at the name of the bus_free_time_cycles field in the i2c_timing_params_t struct and I realized that it is also inconsistent. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
A reviewer on lowRISC#633 commented about inconsistency in the naming of tBUF timing parameter accross different places. That made me look at the name of the bus_free_time_cycles field in the i2c_timing_params_t struct and I realized that it is also inconsistent. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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…vice Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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Added a host Vseq and device SW. The host will initiate read / write transfer. The device SW waits for the transfers to finish and compare the data bytes in each transfer at the end