[top,dv] Add testplan for top-level#668
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marnovandermaas
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marnovandermaas
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My initial review.
| "i2c_host_tx_rx_cheri"] | ||
| } | ||
| { | ||
| name: chip_i2c_device_tx_rx |
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What about i2c host?
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What do you mean? i2c_host is just above.
| SW flushes both FIFOs, acknowledges any pending interrupts, sets threshold | ||
| registers to `MAILBOX_FIFO_DEPTH`, enables all three interrupts, then: | ||
| - Confirms the read FIFO is empty and write FIFO is not full. | ||
| - Writes `MAILBOX_FIFO_DEPTH` elements (0xBEEF0000..N) and confirms the write |
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Why did you chose the value BEEF0000?
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It's just an arbitrary value easy to find in ca log or waves. Do you have another suggestion?
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It's a bit sad that you are adding the image files before they are available. Is there a cleaner way to add a test that is expected to fail?
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I haven't found any other way, and I took this path as it has been mentioned in a meeting that it's good to see some red tests becoming green eventually. I agree with that, then we know directly from a quick glance at the dashboard where we stand. Do you have another suggestion?
Signed-off-by: martin-velay <mvelay@lowrisc.org>
Signed-off-by: martin-velay <mvelay@lowrisc.org>
Signed-off-by: martin-velay <mvelay@lowrisc.org>
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@marnovandermaas, I have implemented most of your feedback and answer to your questions. The comment I've marked as resolved are because I am certain it's addressed. I also did some simplification about the IRQ tests and added a forgotten link to the testplan from the sim_cfg file. |
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Create the full testplan for existing and future tests for top-level DV.