[valassi]

This is a WIP PR for the ideas discussed in the first bullet of #175 (comment)

The idea is to start separating CUDA and C++, so that CUDA does a data access in a large buffer inside the XX functions (and eventually in the FFV functions to split into smaller kernels), while C++ takes a single event or at most a SIMD vector of events.

In practice this means removing ipagV from many interfaces.

Note that ipar is still there for CUDA - this cannot be changed unless/until a new memory structure is introduced, as discussed in the SOAOSOA #309

Note also that ip4 is still in the interface of the bufferAccessMomenta. I think this is unavoidable for CUDA: we want to have an AOSOA for events and 4-components, with a striding not fixed a priori. This also does not harm for c++: it could be avoided as one could just get an fptype_sv[4] and index it in a very intuitive way, but it does not harm to have it as a function.

The same idea could be used eventually for splitting the kernels (#310): it would be enough to add for instance bufferAccessWavefunction( fptype* buffer, int iw6 ) wherethe iw6 index is passed in the same way as the ip4 now.

This is WIP, a lot to do, but the basic idea is there now.

[valassi]

This is now complete thus far and can be merged. Main changes

• removed ipagV and ipar from c++ internal APIs
• started differentiating cuda and c++ (cuda xxx functions dela with large arrays, c++ deals with a single event or event vector)
• renamed and moved indexing functions to MemoryAccess.h
• for the moment, I did keep the complex logic to deal with aligned, unaligned and arbitrary arrays (it can be simplified later on), I actually removed sanity checks and assumptions, and reenabled alignment checks at every call, the overhead is minimal

[valassi]

Self merging