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chore(main): release 0.3.2 - #5

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Mar 24, 2026
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chore(main): release 0.3.2#5
dndungu merged 1 commit into
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🤖 I have created a release beep boop

0.3.2 (2026-03-21)

Bug Fixes

  • cuda: use cgo build tag for arm64 dlopen trampolines (ebff59e)

This PR was generated with Release Please. See documentation.

@dndungu
dndungu merged commit 78fb627 into main Mar 24, 2026
dndungu added a commit that referenced this pull request Jun 12, 2026
…max only (T3.1)

Drop --use_fast_math from NVCC_FLAGS: the flag swapped every
expf/tanhf/logf/division for unsafe approximations library-wide; the
non-saturating fast tanhf caused the GELU blowup behind the GPU f32
CrossAsset cliff (ztensor#125). Per the torch numerics convention
(zerfoo plan-gpu-training-hardening T3.1) fast intrinsics are now
re-enabled selectively in kernel source, only where the PyTorch-oracle
gate proves equivalence within tolerance:

- kernel_softmax keeps __expf AFTER max-subtraction (argument <= 0,
  result in (0,1], ~2^-21 relative error -- inside the Softmax
  tolerance atol 1e-6 / rtol 1e-4).
- Everything else gets the accurate libdevice functions.
- The tanh saturation clamp (ztensor#125) is RETAINED as
  defense-in-depth.

Gate plumbing: oracle-gen grows -engine gpu (GenerateAllWith records
compute.GPUEngine bundles through the same format -- the GPU-side
oracle gate the scripts/oracle README reserved for T3.x), and
compute/gpu_kernel_bench_test.go adds per-kernel GPU micro-benchmarks
for the ops whose codegen changed, for the before/after perf delta.

Verifies zerfoo UC-GH-5.
dndungu added a commit that referenced this pull request Jul 3, 2026
Float32Ops.Sum and Float64Ops.Sum now accumulate in a recursive pairwise
(tree) order whose split points depend only on length, not on chunking.
Bitwise-stable run to run and O(log n) rather than O(n) rounding error,
without narrowing the accumulation dtype. Verifies UC-H2-003 / UC-GH-5.
dndungu added a commit that referenced this pull request Jul 3, 2026
…135.2)

Non-arm64 RMSNormF32 fallback now sums x^2 in fixed-order pairwise float32,
matching the fp32 accumulation of the arm64 NEON path while shrinking the
naive-fold error. The arm64 SIMD path is already fixed-order fp32 (8-way
strided) and is unchanged. Verifies UC-GH-5.
dndungu added a commit that referenced this pull request Jul 3, 2026
…foo T135.2)

Sum/ReduceSum/ReduceMean (via Sum) and the Softmax denominator now use a
fixed-order pairwise tree reduction (compute/reduce_pairwise.go). The
accumulation order is a pure function of the reduced length, so results are
bitwise-identical across GOMAXPROCS and run to run, and agreement with the
PyTorch oracle tightens (16-940x lower float32 relerr for ReduceSum) with no
dtype change. Verifies UC-H2-003 / UC-GH-5.
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