[bong-water-water-bong]

engine#315 candidate 1, part 2 of 2: the pin. Part 1, the switch, is #454.

What moves

• third_party/hrx-system: 2ab311496 -> 82804197b. That is 2ab311496 plus amdgpu: HRX_ALLOW_NO_SVM=1 opens a ROCr that reports no SVM (engine#315) hrx-system#8: util/no_svm_gate.c, where HRX_ALLOW_NO_SVM=1 lets the amdgpu HAL open a ROCr that reports no SVM. Unset, nothing changes.
• config/hrx-system-hold.config names the new commit, so the HRX pins guard passes.
• docs/hrx.md lists Step 3a: NPU full ELFs generated in C++ — no xclbin, no per-context files #8 under "Our hrx-system commits".

Draft until three things are done:

1. hrx-system#8 is merged as a fast-forward, so 82804197b stays the commit on 1bit/e3e6a976-pin-6. If it is squashed, this pin moves to the new sha.
2. tests/hrx_long_prompt.py passes on Strix Halo with this pin and config/hrx-long-prompt-validated-pin.config is moved to 82804197b. That needs GPU time. Until then tools/check_pins.py fails, on purpose: FAIL hrx-system pin 82804197bcbe has not passed the long-prompt check. That is the only failure I get locally.
3. The CWSR-off smoke: on the current boot, serve logs that it did nothing, and HRX output is unchanged against the previous build.

Why a separate PR. #454 checks at configure time whether the hrx-system it builds has the gate. Without the gate, it adds nothing and refuses --hrx-cwsr-placement=on, so the two PRs can merge in either order. This PR is the one that needs GPU validation; #454 does not.

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PR Reviewer Guide 🔍

(Review updated until commit 7a6588f)

Here are some key observations to aid the review process:

🎫 Ticket compliance analysis 🔶 315 - Partially compliant Compliant requirements: The PR updates the hrx-system pin to include the HRX_ALLOW_NO_SVM gate which is a key part of the fix for engine#315 The PR includes documentation updates in docs/hrx.md to reflect the new commit Non-compliant requirements: The PR does not directly address the root cause of the memory fault or NaN logits, but provides the necessary pin to enable the fix The PR does not include actual test results showing the fix working on the hardware Requires further human verification: GPU validation is required to confirm the fix works in practice The CWSR-off smoke test needs to be run to ensure no regression 454 - Partially compliant Compliant requirements: The PR includes the necessary changes to enable CWSR save area placement in GTT The PR updates the hrx-system pin to include the HRX_ALLOW_NO_SVM gate The PR updates documentation to reflect the new functionality Non-compliant requirements: The PR does not include the actual implementation of the CWSR save area placement logic (that's in the other PR) The PR does not include test results showing the fix works Requires further human verification: The CWSR save area placement functionality needs to be tested on actual hardware The tests need to be run on a CWSR-on box to verify the fix 8 - Partially compliant Compliant requirements: The PR updates the hrx-system pin to include the necessary changes for full ELF generation Non-compliant requirements: The PR does not include the actual implementation of full ELF generation (that's in the other PR) Requires further human verification: The full ELF generation functionality needs to be tested on actual hardware

⏱️ Estimated effort to review: 3 🔵🔵🔵⚪⚪

🧪 PR contains tests

🔒 No security concerns identified

⚡ Recommended focus areas for review Pin Update The hrx-system pin has been updated to commit 82804197b, which includes the HRX_ALLOW_NO_SVM gate. This is a necessary dependency for the CWSR save area placement fix, but the actual fix implementation is in a separate PR. The pin update itself is correct, but it's important to note that this change alone does not fix the underlying issue - it enables the fix that will be implemented in the other PR. # 2026-10-18, engine#315 candidate 1: the hold names 82804197b, which is 2ab311496 plus # hrx-system#8 - util/no_svm_gate.c, HRX_ALLOW_NO_SVM=1 lets the amdgpu HAL open a ROCr that # reports no SVM (HSA_USE_SVM=0), so serve can put the CWSR save area in GTT on a CWSR-on box # (app/hrx_cwsr.h). Unset, nothing changes. Same pin line, same AMD core. # The long-prompt check passed at this commit (tests/hrx_long_prompt.py PASS twice, 7082-token # prompt, needle 7341, 2026-10-18 on strixhalo). 82804197bcbe060b1371d6548337fdc842034cdd Documentation Update The documentation has been updated to reflect the new hrx-system commit that includes the HRX_ALLOW_NO_SVM gate. This is important for users to understand what changes are included in the new pin and how they relate to the CWSR save area placement fix. The documentation correctly mentions that the gate allows the amdgpu HAL to open a ROCr that reports no SVM, which is used by 1bit serve to put the CWSR save area in GTT. extent instead of skipping the check); engine#410 (`libhip_intercept` covers every HIP symbol the backend exports, init is idempotent); engine#401 (libhsa no longer opens `/dev/accel` in GPU-only processes); #6 (`generate_stubs.py` takes signatures from `api.h`, so `--check` is trustworthy; regenerated `stubs_generated.c`); #8 (engine#315: `HRX_ALLOW_NO_SVM=1` lets the amdgpu HAL open a ROCr that reports no SVM, which `1bit serve` uses to put the CWSR save area in GTT on a CWSR-on box; unset, nothing changes); and our fix for the long-context attention miscompile ([ROCm/hrx-system#1535](https://github.com/ROCm/hrx-system/issues/1535)): AMD's newer Loom no longer

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Persistent review updated to latest commit aed2ff8

[bong-water-water-bong]

All three draft conditions are now met.

1. hrx-system#8 was merged as a fast-forward, so 1bit/e3e6a976-pin-6 is 82804197b, the commit this PR pins.
2. Long-prompt check: tests/hrx_long_prompt.py passed twice: 7082-token prompt, expected 7341, got 7341.
   • Setup: the engine build's llama-server (llama.cpp 8d9ce2c1a, hrx-system 82804197b), Qwen3-0.6B Q4_K_M, -dev HRX0 -c 8192, strixhalo, performance mode, CWSR-off boot.
   • config/hrx-long-prompt-validated-pin.config now names 82804197b (bd9010c).
   • I merged main in for the Laya bump (Bump Laya: source d74e8be4, model 7b928d82 #452). tools/check_pins.py passes locally and in CI.
3. CWSR-off smoke, 1bit serve -m Qwen3-0.6B-Q4_K_M --device hrx, interleaved old/new/old/new:
   • Builds: new = serve: CWSR save area in GTT when amdgpu runs CWSR on (engine#315 candidate 1) #454's 680183f with hrx-system 82804197b; old = main 8b6a0f4 with 2ab311496.
   • The new build logs 1bit serve: HRX: CWSR is off; CWSR save-area placement unchanged (engine#315). The old build has no such line, as expected.
   • The llama-server child's /proc/<pid>/environ has none of HSA_USE_SVM, HSA_USERPTR_FOR_PAGED_MEM, HRX_ALLOW_NO_SVM, in all 4 runs.
   • 3 identical greedy chat requests per run: all 12 answers are byte-identical (sha f13ce6dd79d2, 423 bytes), old and new.
   • 0 NaN lines.

🤖 Generated with Claude Code

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Persistent review updated to latest commit aed2ff8

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Persistent review updated to latest commit 7a6588f