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[None][feat] MoE scheduler: optional finalize-before-combine and FP4 scale-layout contract fix - #19749
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WalkthroughThe MoE API now accepts a callback that finalizes unfinalized backend output before communication combine. Backend and communication capabilities determine whether this path is supported. FP4 scale handling and FlashInfer provider tests are also updated. ChangesExternal communication finalization
FlashInfer FP4 input handling
Priority: ⬇️ Low Estimated code review effort: 4 (Complex) | ~45 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant Backend as backend.run_moe
participant Scheduler as ExternalCommMoEScheduler
participant Finalizer as unfinalized_combine_fn
participant Comm as comm.combine
Backend->>Scheduler: Return unfinalized output
Scheduler->>Finalizer: Finalize dispatched rows
Finalizer-->>Scheduler: Return finalized output
Scheduler->>Comm: Combine finalized output
Suggested reviewers: Merge Risk: 🔵 Low · up to The new multi-GPU finalization comparison is not exercised in the inspected CI lists. Confirm its intended CI or QA status before merging. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 55.81% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 86 functions across 15 files. (1 skipped: 1 unsupported.)
✨ Finishing Touches🧪 Generate unit tests (beta)
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- Line 100: Update the test’s pytest skip condition around
torch.cuda.is_available() to require the pinned FlashInfer provider’s supported
CUDA version and GPU architecture before warmup; keep failures visible when
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🟡 Minor · Preserve a 2-D scale for zero-token FlashInfer calls. · moe_op_backend.py:797-805
tensorrt_llm/_torch/moe/fused_moe/moe_op_backend.py:797-805
🩺 Stability & Availability | 🟡 Minor | ⚡ Quick winPreserve a 2-D scale for zero-token FlashInfer calls.
When a zero-token FP4 chunk reaches this path,
prepare_kernel_inputsflattensx_sfto(0,). Thetokens > 0guard then skips the reshape, andrun_fp4_block_scale_moeforwards that rank-1 tensor to FlashInfer. FlashInfer 0.6.18 documents the activation scale as[seq_len, hidden_size // 16], so the zero-token shape must retain two dimensions. The call can therefore violate the provider contract and fail.Handle the zero-token branch before the FlashInfer call and pass a token-major empty scale with the documented shape. The mock test does not validate this provider behavior.
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Review comments at @tensorrt_llm/_torch/moe/fused_moe/moe_op_backend.py:
- Around line 797-805: In the zero-token branch before the FlashInfer call in
the `router_logits` path, ensure `hidden_states_scale` remains token-major with
shape `(0, hidden_size // 16)` instead of forwarding a rank-1 tensor. Preserve
the existing reshape behavior for nonzero token counts.
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…contract fix Scheduler: do_finalize=False asks the backend for the unfinalized (gemm2_output, expert_weights, expanded_idx_to_permuted_idx) triple so a model can apply its own per-(token, expert) transform to each expert output before the top-k sum. Every Communication.combine is typed for a dense per-token tensor, so that triple cannot cross a comm strategy today. Add ConfigurableMoE.unfinalized_combine_fn: a model registers its per-row finalize there, and ExternalCommMoEScheduler runs it on the dispatched rows just before the combine, so the combine reduces already-finalized partials. That reordering equals finalizing after the combine because each term depends on one (token, expert) row alone and non-local slots contribute exact zeros. The unsupported combination (do_finalize=False with an active comm strategy and no registered finalize) becomes a named refusal instead of an AttributeError deep in the comm layer. The NVLinkOneSided workspace plan also stops claiming the combine payload is in the alltoall workspace for do_finalize=False: the backend writes no payload in that mode, and combine() trusts the flag rather than the tensor argument, so a stale True would make moe_a2a_combine reduce an unwritten workspace region silently. FlashInfer FP4 scale layout, opt-in via TRTLLM_FLASHINFER_FP4_CONTRACT_FIX=1: fp4_quantize provider options are passed by keyword (new provider options may precede enable_pdl in the positional signature), and a flattened linear hidden_states_scale is re-viewed token-major as (num_tokens, -1) float8_e4m3fn before trtllm_fp4_block_scale_moe, whose API requires the leading dimension to be num_tokens. Default behavior is unchanged. Covered by CPU unit tests with fake backends/providers: a scheduler test for the finalize-before-combine seam (happy path plus the four refusals) and a FlashInfer scale-layout test; one opt-in CUDA-graph case runs only when a GPU is available. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
CUDA availability alone does not establish FP4 provider support: FlashInfer's FP4 quantization has no backend for pre-Blackwell architectures, so the opt-in real-provider test failed with an invalid backend error on SM80/SM86. Use the standard skip_pre_blackwell marker, matching the repo's FP4 capability convention. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
…rameter _build_comm_plan now takes a required do_finalize argument; the pre-existing deep-EP direct-metadata scheduler test still called it without one and failed with a TypeError on Blackwell CI. Pass do_finalize=True, matching the fused-finalize path the test exercises. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
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Thanks for the contribution, could you help to address the comments?
The pinned flashinfer-python places is_global_scale_inversed before enable_pdl, so the positional fp4_quantize call misbinds it, and its MoERunner asserts a 2-D activation scale with shape[0] == num_tokens. The TRTLLM_FLASHINFER_FP4_CONTRACT_FIX flag therefore guarded the only working path; drop it and make both fixes unconditional. Keep x_sf token-major 2-D as quantize_input produces it instead of flattening in the provider-neutral kernel-input assembly and undoing it in the FlashInfer runner. The flat 1-D linear layout is a native-ABI requirement (fp4BlockScaleMoe.cpp checks dim() == 1), so TRTLLMOpBackend flattens inside its own kernel-facing method. This also removes the tokens == 0 special case: an empty 2-D scale passes through unchanged. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
…argument Register the model-owned finalize through create_moe(..., unfinalized_combine_fn=...), guarded like communication_method, instead of poking an attribute onto the layer. ConfigurableMoE.validate_backend (which runs after self.comm exists) rejects every configuration the contract cannot hold under: a backend that cannot return the unfinalized triple (new supports_unfinalized_output() capability, declared by the NVFP4, W4A8 NVFP4xFP8, and FlashInfer BF16 TRTLLM-Gen leaves), a comm strategy whose combine is not an unweighted row sum over a dense per-token tensor (new Communication.supports_finalize_before_combine(); DeepEPLowLatency answers False because its combine consumes expert-major rows and applies the routing weights itself), and apply_router_weight_on_input (the dispatched token_final_scales are then placeholders). Once registered, the hook now runs on every do_finalize=False forward, with or without a comm strategy, so the forward's return type depends only on static config -- call sites that unpack the triple and the List[Tensor] contract of trtllm::moe_custom_op see one return type per configuration. The scheduler also passes token_selected_slots to the hook (a per-expert transform cannot tell which expert a row belongs to without it) and asserts the output is [num_tokens, hidden_size], since gemm2_output is hidden-padded and the hook owns the slice. The developer guide paragraph claiming every combine takes a dense per-token tensor is updated to describe the capability instead. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
…est files test_flashinfer_moe_scale_layout.py modeled a provider signature that is not the pinned one and parametrized over a flag that no longer exists; the real coverage gap was that no default configuration ever runs the quantized FlashInfer provider. Replace it with a real-provider NVFP4 case in test_moe_backend.py (create_test_backend grows a moe_cls pin, since resolution always prefers the native leaf when one exists). test_moe_scheduler_finalize_before_combine.py dissolves into the existing files: the NVLinkOneSided workspace-plan cases sit next to the other _build_comm_plan test in test_moe_backend.py, the refusals that moved to construction become validate_backend tests, and the scheduler finalize tests pick up the new token_selected_slots argument and the [num_tokens, hidden_size] output check. A numerical check that a registered hook under a real communication strategy reproduces the in-kernel finalize (do_finalize=False vs do_finalize=True) joins the multi-GPU cases in test_moe_module.py. Signed-off-by: Brian Nguyen <brnguyen@nvidia.com>
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- Around line 1992-2006: Add
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tensorrt_llm/_torch/moe/fused_moe/MOE_DEVELOPER_GUIDE.mdtensorrt_llm/_torch/moe/fused_moe/communication/base.pytensorrt_llm/_torch/moe/fused_moe/communication/deep_ep_low_latency.pytensorrt_llm/_torch/moe/fused_moe/configurable_moe.pytensorrt_llm/_torch/moe/fused_moe/create_moe.pytensorrt_llm/_torch/moe/fused_moe/impl_blocks.pytensorrt_llm/_torch/moe/fused_moe/moe_op_backend.pytensorrt_llm/_torch/moe/fused_moe/moe_scheduler.pytensorrt_llm/_torch/moe/fused_moe/trtllm_gen/flashinfer_bf16.pytensorrt_llm/_torch/moe/fused_moe/trtllm_gen/fp4_block_scale.pytensorrt_llm/_torch/moe/fused_moe/trtllm_gen/kernel_inputs.pytensorrt_llm/_torch/moe/fused_moe/trtllm_gen/trtllm_w4a8_nvfp4_fp8.pytests/unittest/_torch/moe/test_moe_backend.pytests/unittest/_torch/moe/test_moe_module.py
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Main's NVIDIA#19896 (2681ed1) moved PyTorchModelEngine's decoder execution into DecoderRunner (engine/runners/decoder/runner.py) and the encoder-decoder fast path into EncoderDecoderRunner, so this branch's model_engine.py changes conflicted. model_engine.py is main's; the branch's changes move to where that code now lives: - DecoderRunner, from NVIDIA#19816 (U1): the step-copy gather, the staged previous batch / position indices, gather_ids written by copy_to_device_if_changed, no num_accepted_draft_tokens buffer, and the CUDA graphs' static inputs; from NVIDIA#19814 (U3): the gather of vocabulary-sharded logits for post-processors. - EncoderDecoderRunner: its previous_batch_indices_cuda write clears the staged batch indices. - The two tests that called the moved members call the runner. Main's other commits since f891b3d: NVIDIA#19484, NVIDIA#19892, NVIDIA#19409, NVIDIA#19553, NVIDIA#19957, NVIDIA#19749, NVIDIA#19585, NVIDIA#19766, NVIDIA#19963, NVIDIA#19588, NVIDIA#19600, NVIDIA#19825, NVIDIA#19821, NVIDIA#19930, NVIDIA#18485. Signed-off-by: Vasanth Sabavat <vsabavat@nvidia.com>
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Dev Engineer Review
The only current diff reformats the
.moe_resolutionimport increate_moe.py. It does not change API behavior or runtime logic.QA Engineer Review
No test changes.
Per-File QA Perspective
tensorrt_llm/_torch/moe/fused_moe/create_moe.py: The import formatting change introduces no observable behavior for QA to verify.Description
Two independent pieces, both in the ConfigurableMoE stack.
1. Scheduler: optional model-owned finalize before the communication
combine.
do_finalize=Falseasks the backend for the unfinalized(gemm2_output, expert_weights, expanded_idx_to_permuted_idx)triple so amodel can apply its own per-
(token, expert)transform to each expertoutput before the top-k sum. Every
Communication.combineis typed for adense per-token tensor, so that triple cannot cross a comm strategy today —
it reaches
.dim()on alistand dies several frames inside the commlayer. This PR adds
ConfigurableMoE.unfinalized_combine_fn: a modelregisters its per-row finalize there, and
ExternalCommMoESchedulerruns iton the dispatched rows just before the combine, so the combine reduces
already-finalized partials. The reordering equals finalizing after the
combine because each term depends on one
(token, expert)row alone andnon-local slots contribute exact zeros. With no registered finalize, the
do_finalize=False+ active-comm combination becomes a namedNotImplementedErrorinstead of a crash in the comm layer.The
NVLinkOneSidedworkspace plan also stops claiming the combine payloadis in the alltoall workspace when
do_finalize=False: the backend writes nopayload in that mode, and
combine()trusts the flag rather than the tensorargument, so a stale
Truewould makemoe_a2a_combinereduce an unwrittenworkspace region and silently return garbage.
No in-tree model registers the hook yet; today every in-tree caller keeps
do_finalize=Falseand comm strategies apart. The mechanism is the genericscheduler contract for any backend/model that wants finalize to run inside a
communication-overlap region; default behavior is unchanged.
2. FlashInfer MoE FP4 scale-layout contract fix (opt-in via
TRTLLM_FLASHINFER_FP4_CONTRACT_FIX=1). Two call-contract fixes inFlashinferOpBackend:fp4_quantizeprovider options are passed by keyword(new provider options may precede
enable_pdlin the positional signature,so positional passing can silently bind the wrong argument), and a flattened
linear
hidden_states_scaleis re-viewed token-major as(num_tokens, -1)float8_e4m3fnbeforetrtllm_fp4_block_scale_moe, whose API requires theleading dimension to be
num_tokens. The flag is resolved once at backendconstruction (before warmup/capture); default off, zero behavior change.
Test Coverage
tests/unittest/_torch/moe/test_moe_scheduler_finalize_before_combine.py— CPU-only, stubbed
moe/comm objects: happy path (finalize receives thebackend triple, the post-dispatch routing weights, the dispatched row
count; output cast down before the combine) plus the four refusals
(unregistered finalize, backend that ignored
do_finalize, router weightsfolded into activations, weights/index-map row mismatch) and both sides of
the one-sided workspace-payload guard.
tests/unittest/_torch/moe/test_flashinfer_moe_scale_layout.py— fakeprovider: keyword binding of
fp4_quantizeoptions under flag on/off/unsetand token-major scale reshaping (0/1/2/16 tokens, routed and unrouted,
flattened and matrix input, zero-copy asserted via
data_ptr). OneGPU-gated case checks the opt-in path against the real provider under CUDA
graph capture/replay.
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