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Add the movdir64b and movdiri x86 target features - #163742
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`MOVDIR64B` and `MOVDIRI` (direct stores of 64 bytes and of a 32/64-bit integer) are standalone x86 CPUID features, on Intel Tiger Lake and Sapphire Rapids onwards and AMD Zen 5, that are not part of any psABI microarchitecture level. They need their own unstable target features, gated behind `movdir64b_target_feature` and `movdiri_target_feature`. This is the compiler half of exposing the `_movdir64b`, `_directstoreu_u32` and `_directstoreu_u64` intrinsics; the stdarch half is blocked on this landing. Also update the check-cfg/target_feature UI test reference, which enumerates the full set of valid target features.
Wire up runtime detection for both features: add them to the `is_x86_feature_detected!` feature list (gated on `movdir64b_target_feature` and `movdiri_target_feature`), enable them from CPUID leaf 7 ECX bits 28 and 27, and add them to the std_detect x86-specific dump test.
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Target features are being changed; ensure all ABI effects are being accounted for cc @RalfJung Some changes occurred in cc @Amanieu, @folkertdev, @sayantn |
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@bors r+ rollup |
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…=folkertdev
Add the `movdir64b` and `movdiri` x86 target features
Adds the unstable `movdir64b` and `movdiri` x86 target features, gated behind `#![feature(movdir64b_target_feature)]` and `#![feature(movdiri_target_feature)]`, and runtime detection with `is_x86_feature_detected!("movdir64b")` / `is_x86_feature_detected!("movdiri")` (CPUID.(EAX=7,ECX=0):ECX[28] and ECX[27]).
`MOVDIR64B` moves 64 bytes from memory to a 64-byte aligned destination as a single direct store; `MOVDIRI` stores a 32- or 64-bit integer as a direct store. Both are on Intel Tiger Lake / Alder Lake and later, Sapphire Rapids and later Xeons, and AMD Zen 5. They're standalone CPUID features that aren't part of any psABI microarchitecture level, so they need their own feature flags.
**This is the compiler half of a two-PR feature, like `clflushopt` in rust-lang#157098.** The `_movdir64b`, `_directstoreu_u32` and `_directstoreu_u64` intrinsics (rust-lang/stdarch#2239) can't compile until these target features exist, so the stdarch PR is blocked on this one merging and syncing into stdarch's pinned toolchain.
- Tracking issue: rust-lang#163741
- Unblocks intrinsics: rust-lang/stdarch#2239
Today the only way to emit these instructions from Rust is `asm!`, which also hides them from LLVM: a copy loop through `llvm.x86.movdir64b` gets unrolled and the source address becomes a displacement, while the `asm!` version stays one instruction per iteration with both addresses in registers.
`movdir64b` and `movdiri` are LLVM's feature names, so they map 1:1 through `to_llvm_features` with no remap entry. I ran the two new feature-gate tests, `check-cfg/target_feature` and `target-feature/invalid-attribute`, the std_detect tests (which report both features as `true` on a Xeon 6975P-C), and tidy locally on x86_64-pc-windows-msvc.
r? @folkertdev
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…uwer Rollup of 6 pull requests Successful merges: - #161491 (Rip out old solver coherence) - #163223 (regression test for async handler normalization ICE) - #163653 (callconv: mips64: Match GCC for alignment of 16-byte scalars) - #163742 (Add the `movdir64b` and `movdiri` x86 target features) - #163752 (Revert "implement PartialEq<VecDeque<U>> for Vec<T>, &[T], &mut [T], [T; N], &[T; N] and &mut [T; N]") - #163755 (fix -Z track-diagnostics for errors and lints emitted from rustc_attr_parsing)
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…uwer Rollup of 9 pull requests Successful merges: - #161491 (Rip out old solver coherence) - #163533 (Run cg_gcc tests with the correct compiler) - #163223 (regression test for async handler normalization ICE) - #163367 (simplify rustc_log a bit) - #163622 (x86: c-variadic functions don't use registers with `-Zregparm`) - #163653 (callconv: mips64: Match GCC for alignment of 16-byte scalars) - #163665 (Parser: Refactor & better document `should_continue_as_assoc_expr` & `can_continue_expr_unambiguously`) - #163742 (Add the `movdir64b` and `movdiri` x86 target features) - #163752 (Revert "implement PartialEq<VecDeque<U>> for Vec<T>, &[T], &mut [T], [T; N], &[T; N] and &mut [T; N]")
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Rollup merge of #163742 - jlpetz:movdir64b-target-feature, r=folkertdev Add the `movdir64b` and `movdiri` x86 target features Adds the unstable `movdir64b` and `movdiri` x86 target features, gated behind `#![feature(movdir64b_target_feature)]` and `#![feature(movdiri_target_feature)]`, and runtime detection with `is_x86_feature_detected!("movdir64b")` / `is_x86_feature_detected!("movdiri")` (CPUID.(EAX=7,ECX=0):ECX[28] and ECX[27]). `MOVDIR64B` moves 64 bytes from memory to a 64-byte aligned destination as a single direct store; `MOVDIRI` stores a 32- or 64-bit integer as a direct store. Both are on Intel Tiger Lake / Alder Lake and later, Sapphire Rapids and later Xeons, and AMD Zen 5. They're standalone CPUID features that aren't part of any psABI microarchitecture level, so they need their own feature flags. **This is the compiler half of a two-PR feature, like `clflushopt` in #157098.** The `_movdir64b`, `_directstoreu_u32` and `_directstoreu_u64` intrinsics (rust-lang/stdarch#2239) can't compile until these target features exist, so the stdarch PR is blocked on this one merging and syncing into stdarch's pinned toolchain. - Tracking issue: #163741 - Unblocks intrinsics: rust-lang/stdarch#2239 Today the only way to emit these instructions from Rust is `asm!`, which also hides them from LLVM: a copy loop through `llvm.x86.movdir64b` gets unrolled and the source address becomes a displacement, while the `asm!` version stays one instruction per iteration with both addresses in registers. `movdir64b` and `movdiri` are LLVM's feature names, so they map 1:1 through `to_llvm_features` with no remap entry. I ran the two new feature-gate tests, `check-cfg/target_feature` and `target-feature/invalid-attribute`, the std_detect tests (which report both features as `true` on a Xeon 6975P-C), and tidy locally on x86_64-pc-windows-msvc. r? @folkertdev
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- Each crate carries LICENSE-APACHE and LICENSE-MIT, so `cargo package` includes them. - plumb_tiles' example is now `tile_kernels`; both crates had an example called `asm_kernels`. - README gains an Upstream section, and the docs link the PRs that would retire `asm!`: llvm/llvm-project#229240 for NT stores, rust-lang/rust#163742 and rust-lang/stdarch#2239 for MOVDIR64B, and llvm/llvm-project#229025 for the AMX intrinsics' memory effects. - TODO 1 closes (first CI runs green); TODO 5 records #228875's close and the fixes offered on #229240. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Adds the unstable
movdir64bandmovdirix86 target features, gated behind#![feature(movdir64b_target_feature)]and#![feature(movdiri_target_feature)], and runtime detection withis_x86_feature_detected!("movdir64b")/is_x86_feature_detected!("movdiri")(CPUID.(EAX=7,ECX=0):ECX[28] and ECX[27]).MOVDIR64Bmoves 64 bytes from memory to a 64-byte aligned destination as a single direct store;MOVDIRIstores a 32- or 64-bit integer as a direct store. Both are on Intel Tiger Lake / Alder Lake and later, Sapphire Rapids and later Xeons, and AMD Zen 5. They're standalone CPUID features that aren't part of any psABI microarchitecture level, so they need their own feature flags.This is the compiler half of a two-PR feature, like
clflushoptin #157098. The_movdir64b,_directstoreu_u32and_directstoreu_u64intrinsics (rust-lang/stdarch#2239) can't compile until these target features exist, so the stdarch PR is blocked on this one merging and syncing into stdarch's pinned toolchain.movdir64b_target_featureandmovdiri_target_feature#163741_movdir64b,_directstoreu_u32and_directstoreu_u64intrinsics stdarch#2239Today the only way to emit these instructions from Rust is
asm!, which also hides them from LLVM: a copy loop throughllvm.x86.movdir64bgets unrolled and the source address becomes a displacement, while theasm!version stays one instruction per iteration with both addresses in registers.movdir64bandmovdiriare LLVM's feature names, so they map 1:1 throughto_llvm_featureswith no remap entry. I ran the two new feature-gate tests,check-cfg/target_featureandtarget-feature/invalid-attribute, the std_detect tests (which report both features astrueon a Xeon 6975P-C), and tidy locally on x86_64-pc-windows-msvc.r? @folkertdev