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[https://nvbugs/6921137][fix] Fix CuTe MLA page-table batch bounds - #20256

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pengbowang-nv:fix/cute-mla-active-batch-6923600
Oct 15, 2026
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pengbowang-nv merged 4 commits into
NVIDIA:mainfrom
pengbowang-nv:fix/cute-mla-active-batch-6923600

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@pengbowang-nv pengbowang-nv commented Oct 14, 2026 •

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Dev Engineer Review

_run_mla_decode now selects page-table rows from meta.num_contexts through meta.num_contexts + batch_size. This preserves the context-prefix offset and limits the selected rows to the active decode batch. The transpose, int32 conversion, and kernel API remain unchanged.

QA Engineer Review

tests/integration/test_lists/waives.txt removes ten waivers: six DeepSeek R1 throughput and NVFP4 entries, one DeepSeek V3 Lite FP8 NIXL disaggregation entry, and three KV-cache V2 scheduler MTP entries. No test code or regression test was added. Supplied CI reports include failed runs and an unstable, partly tested run, but do not identify the failing tests. GPU correctness remains unverified. Coverage verdict: needs follow-up.

Per-File QA Perspective

  • tensorrt_llm/_torch/attention/backends/fmha/cute_dsl_mla.py: Verify page-table selection with context prefixes and active batches smaller than buffer capacity. Confirm the kernel launch batch matches the active Q, output, and sequence-length tensors.
  • tests/integration/test_lists/waives.txt: Ten waivers were removed across DeepSeek R1, DeepSeek V3 Lite disaggregation, and KV-cache V2 scheduler tests. Verify these cases run successfully without the waivers.

Description

Fixes NVBug 6923600.

The CuTe MLA adapter slices the generation page table without a stop bound, so a capacity-sized metadata buffer can pass more rows than the active generation batch. Both the FP16 and FP8 kernels derive their launch batch from the page-table shape, which can schedule requests beyond the active Q, output, and sequence-length tensors.

Bound the slice to [num_contexts:num_contexts + batch_size], preserving the context prefix offset and the existing transpose and dtype conversion. This fixes the adapter contract exposed by #19338 without changing the kernel API.

Test Coverage

  • Passed the project pre-commit hooks for cute_dsl_mla.py, including Ruff lint and formatting.
  • Passed five source slice-expression checks, including capacity 128 / active batch 112 with context prefixes 0 and 3, full capacity, a slice ending at capacity, and a single generation request. These checks validate row selection only, not GPU execution.
  • GPU validation and full model reproduction are not included in these results.

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  • Documentation updated as needed

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  • Please check this after reviewing the above items as appropriate for this PR.

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Walkthrough

The MLA decode path now selects exactly the page-table rows for the decode batch, starting after the context rows. The integration test waiver list removes skip entries for DeepSeek throughput and NIXL disaggregation tests, and KV-cache V2 scheduler tests.

Changes

MLA decode page-table selection

Layer / File(s) Summary
Select decode batch rows
tensorrt_llm/_torch/attention/backends/fmha/cute_dsl_mla.py
The page-table slice selects batch_size rows after the context rows before transposing and converting them to int32.

Integration test waivers

Layer / File(s) Summary
Remove integration test waivers
tests/integration/test_lists/waives.txt
The list removes six DeepSeek R1 throughput/NVFP4 skip entries, one DeepSeek V3 Lite FP8 NIXL disaggregation entry, and three KV-cache V2 scheduler entries.

Priority: ➖ Normal

Estimated code review effort: 2 (Simple) | ~10 minutes

Change: Bug fix

Suggested reviewers: bowenfu

Merge Risk: ⚪ Minimal · up to a85ad

The MLA row selection matches the active decode batch. No concrete issue remains that warrants blocking merge beyond normal CI checks.

Pre-merge checks: Passed 4 · Failed 1

Failed Failed checks: 1 warning

Check name Status Explanation Resolution
Docstring Coverage Warning Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 1 functions across 1 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
Passed Passed checks: 4 passed
Check name Status Explanation
Title check Passed The title is concise, specific, and accurately describes the CuTe MLA page-table bounds fix.
Description check Passed The description explains the issue, solution, test coverage, and checklist status. It also clearly states that GPU validation and full model reproduction were not performed.
Linked Issues check Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check Passed Check skipped because no linked issues were found for this pull request.
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Actionable comments posted: 1


  • 🪄 Fix CodeRabbit comments on this PR
🤖 Prompt to fix review comments
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Inline comments:
Review comments at @tensorrt_llm/_torch/attention/backends/fmha/cute_dsl_mla.py:
- Line 466: Add focused regression coverage for _run_mla_decode that captures
the page table passed to the decode operation and verifies it contains only rows
3 through 114, transposed and converted to int32. Use capacity 128,
num_contexts=3, and batch_size=112 so the test fails if the slice includes all
rows after the context prefix.

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  • tensorrt_llm/_torch/attention/backends/fmha/cute_dsl_mla.py

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Comment thread tensorrt_llm/_torch/attention/backends/fmha/cute_dsl_mla.py
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PR_Github #77668 [ run ] triggered by Bot. Commit: aeb86d5 Link to invocation

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yuxianq commented Oct 14, 2026 •

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@yihwang-nv, could you help to review this PR as trt-llm-torch-attention-devs? Thanks~

Assignment explanation
Componentsfmha/cute-dsl-mla (100%)
Tagsrepresentation:mla (100%); phase:decode (100%); features:paged-kv (100%)
PR effort3 points — A small adapter fix requires checking the context offset and active-batch bound against the downstream launch contract. Missing executable regression coverage adds review effort despite the minimal diff.
ImportanceImportant — The changed slice limits the page-table dimension that the visible comment identifies as determining kernel launch batch. This is a sensitive correctness boundary between active requests and metadata capacity.
Affinity (0–1)0.574 component/tag match; 0.430 after PIC preference
Outstanding points at selection47 → 50 (+3)
Points already reserved on this PR0
Effective weight1
Completed review points (preceding 168 hours)28
Combined points after assignment78
Demand-derived target72.00 points (soft share)
Additional fair share before assignment0.00 points
Share explanationWhole PR / qualification or coverage constraint exceeds a soft share; assignment is allowed.
Selection ruleaffinity with half-share guard

Affinity and workload are snapshots at selection, not live counters. Existing reservations on this PR are counted once.

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yuxianq requested review from yihwang-nv and removed request for farazkh80 and kris1025 October 14, 2026 03:53
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PR_Github #77668 [ run ] completed with state FAILURE. Commit: aeb86d5
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LGTM

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Automatically added "ci: full pre-merge approved" because this PR has satisfied the required GitHub review approvals. Unresolved review conversations and other required checks remain independent merge requirements.

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/bot run --stage-list "DGX_B200-2_GPUs-PyTorch-1"

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PR_Github #77682 [ run ] triggered by Bot. Commit: aeb86d5 Link to invocation

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/bot run --stage-list "DGX_B200-2_GPUs-PyTorch-1"

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PR_Github #77682 [ run ] completed with state FAILURE. Commit: aeb86d5
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PR_Github #77687 [ run ] triggered by Bot. Commit: aeb86d5 Link to invocation

@pengbowang-nv pengbowang-nv changed the title [https://nvbugs/6923600][fix] Fix CuTe MLA page-table batch bounds [https://nvbugs/6921137][fix] Fix CuTe MLA page-table batch bounds Oct 14, 2026
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/bot run --stage-list "DGX_B200-2_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-3,GB200-8_GPUs-2_Nodes-PyTorch-2"

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/bot run --stage-list "DGX_B200-2_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-3,GB200-8_GPUs-2_Nodes-PyTorch-2,DGX_B300-4_GPUs-PyTorch-1,DGX_B200-4_GPUs-PyTorch-1"

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/bot run --stage-list "DGX_B200-2_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-2,DGX_B200-8_GPUs-PyTorch-3,GB200-8_GPUs-2_Nodes-PyTorch-1,GB200-8_GPUs-2_Nodes-PyTorch-2,DGX_B300-4_GPUs-PyTorch-1,DGX_B200-4_GPUs-PyTorch-1,DGX_B200-4_GPUs-PyTorch-Post-Merge-1,DGX_B300-4_GPUs-PyTorch-Post-Merge-2,GB300-4_GPUs-PyTorch-Post-Merge-3,GB200-8_GPUs-2_Nodes-PyTorch-Post-Merge-3,DGX_B200-8_GPUs-PyTorch-PerfSanity-Post-Merge-3"

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PR_Github #77712 [ run ] triggered by Bot. Commit: 1a2f257 Link to invocation

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PR_Github #77687 [ run ] completed with state ABORTED. Commit: aeb86d5

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/bot run --extra-stage "DGX_B200-2_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-1,DGX_B200-8_GPUs-PyTorch-2,DGX_B200-8_GPUs-PyTorch-3,GB200-8_GPUs-2_Nodes-PyTorch-1,GB200-8_GPUs-2_Nodes-PyTorch-2,DGX_B300-4_GPUs-PyTorch-1,DGX_B200-4_GPUs-PyTorch-1,DGX_B200-4_GPUs-PyTorch-Post-Merge-1,DGX_B300-4_GPUs-PyTorch-Post-Merge-2,GB300-4_GPUs-PyTorch-Post-Merge-3,GB200-8_GPUs-2_Nodes-PyTorch-Post-Merge-3,DGX_B200-8_GPUs-PyTorch-PerfSanity-Post-Merge-3" --disable-fail-fast

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PR_Github #77712 [ run ] completed with state SUCCESS. Commit: 1a2f257
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PR_Github #77768 [ run ] triggered by Bot. Commit: 1a2f257 Link to invocation

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pengbowang-nv enabled auto-merge (squash) October 14, 2026 09:42
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PR_Github #77768 [ run ] completed with state SUCCESS. Commit: 1a2f257
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pengbowang-nv force-pushed the fix/cute-mla-active-batch-6923600 branch from 1a2f257 to a85adee Compare October 14, 2026 14:42
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/bot run --disable-fail-fast --extra-stage "DGX_B200-2_GPUs-PyTorch-1"

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PR_Github #77833 [ run ] triggered by Bot. Commit: a85adee Link to invocation

Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
…ion cases

Signed-off-by: Pengbo Wang <221450789+pengbowang-nv@users.noreply.github.com>
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pengbowang-nv force-pushed the fix/cute-mla-active-batch-6923600 branch from a85adee to 95f3556 Compare October 14, 2026 18:22
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/bot run --disable-fail-fast

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/bot run --disable-fail-fast

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PR_Github #77900 [ run ] triggered by Bot. Commit: 95f3556 Link to invocation

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PR_Github #77833 [ run ] completed with state ABORTED. Commit: a85adee

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PR_Github #77900 [ run ] completed with state SUCCESS. Commit: 95f3556
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pengbowang-nv merged commit e87862c into NVIDIA:main Oct 15, 2026
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chenfeiz0326 added a commit to chenfeiz0326/TensorRT-LLM that referenced this pull request Oct 15, 2026
…test

NVIDIA#20256 limited the page table CuteDslMlaFmha._run_mla_decode passes to
the CuTe DSL MLA decode kernel to this batch's generation rows; with
max_num_sequences columns the kernel launched one request per column and
read q, the output and the sequence lengths past their ends (illegal
address in the first Kimi-K3 helix warmup forward on GB300).

On top of that:
- Slice sequence_lengths to the batch as well, so every operand the
  kernel receives has the same batch size.
- CuteDSLNVMlaDecodeBlackwellRunner.forward now raises if page_table, q
  or the output disagrees with cache_seqs on the batch dimension, so a
  mismatched caller fails with a message instead of reading out of
  bounds.
- Add test_cute_dsl_mla_decode_batch_below_max_num_sequences: runs
  _run_mla_decode with a 32-slot block table and a batch of 1 or 3 at
  the Kimi-K3 helix verify-group shape (H=96, 7 query tokens, per-token
  kv_bounds), bf16 and fp8, against a reference. It fails on the
  pre-NVIDIA#20256 slice and passes now.

Signed-off-by: chenfeiz0326 <203214996+chenfeiz0326@users.noreply.github.com>
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